RTL NN加速器的恢复力：故障特征和缓解
On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation
摘要：
机器学习（ML）正在与大量生成的非结构化数据保持一致，这反过来又需要大量的计算资源。由于神经网络（NN）固有的计算和功耗密集型结构，硬件加速器成为一种有前途的解决方案。然而，随着技术节点扩展到10 nm以下，硬件加速器变得更容易出现故障，这反过来会影响NN的准确性。在本文中，我们研究了寄存器传输级（RTL）模型的NN加速器的弹性方面，特别是，故障表征和缓解。通过以下的高层次综合（HLS）的方法，首先，我们的RTL神经网络的各个组件的脆弱性的特征。我们观察到故障的严重性取决于i）应用级规范，即，NN数据（输入、权重或中间）、NN层和NN激活函数，以及ii）架构级规范，即，数据表示模型和底层加速器的并行度。其次，由表征结果的动机，我们提出了一种低开销的故障缓解技术，可以有效地纠正位翻转，比最先进的方法好47.3%。
英文摘要：
Machine Learning (ML) is making a strong resurgence in tune with the massive generation of unstructured data which in turn requires massive computational resources. Due to the inherently compute- and power-intensive structure of Neural Networks (NNs), hardware accelerators emerge as a promising solution. However, with technology node scaling below 10nm, hardware accelerators become more susceptible to faults, which in turn can impact the NN accuracy. In this paper, we study the resilience aspects of Register-Transfer Level (RTL) model of NN accelerators, in particular, fault characterization and mitigation. By following a High-Level Synthesis (HLS) approach, first, we characterize the vulnerability of various components of RTL NN. We observed that the severity of faults depends on both i) application-level specifications, i.e., NN data (inputs, weights, or intermediate), NN layers, and NN activation functions, and ii) architectural-level specifications, i.e., data representation model and the parallelism degree of the underlying accelerator. Second, motivated by characterization results, we present a low-overhead fault mitigation technique that can efficiently correct bit flips, by 47.3% better than state-of-the-art methods.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
