再论高层次综合中动态数据流行为对分子动力学模拟的FPGA加速
Revisiting FPGA Acceleration of Molecular Dynamics Simulation with Dynamic Data Flow Behavior in High-Level Synthesis
摘要：
分子动力学（MD）模拟是过去十年中生物科学家和研究人员探索人类健康和疾病的最重要工具之一。然而，由于MD算法的计算复杂性，在传统的多核处理器上模拟相对简单的生物实体需要数周甚至数月。分子动力学模拟中的关键路径是模拟环境中粒子间的力的计算，具有丰富的并行性。在众多的加速平台中，FPGA以其低功耗、高能效的特点成为一个极具吸引力的选择。然而，由于其使用RTL的编程成本高，还没有主流的MD软件包采用FPGA进行加速。在本文中，我们重新审视的高层次综合（HLS）的MD的FPGA加速，以提供负担得起的编程成本。我们的MD加速经验表明，HLS优化，如循环流水线，模块复制和内存分区是必不可少的，以提高性能，实现了9.5倍的加速比相比，12核CPU。更重要的是，我们观察到，即使是完全优化的HLS设计仍然可能比参考RTL架构慢2倍，这是由于当前HLS工具尚未支持的常见动态（条件）数据流行为。为了支持这种行为，我们通过一个通用的RTL模板进一步定制了一系列处理元素以及一个数据驱动的流网络，并完全自动化了设计流程。我们的最终实验结果表明，与12核英特尔至强服务器相比，在Convey HC1ex FPGA上广泛使用的ApoA1 MD基准测试的性能加速为19.4倍，能效为39倍。
英文摘要：
Molecular dynamics (MD) simulation is one of the past decade's most important tools for enabling biology scientists and researchers to explore human health and diseases. However, due to the computation complexity of the MD algorithm, it takes weeks or even months to simulate a comparatively simple biology entity on conventional multicore processors. The critical path in molecular dynamics simulations is the force calculation between particles inside the simulated environment, which has abundant parallelism. Among various acceleration platforms, FPGA is an attractive alternative because of its low power and high energy efficiency. However, due to its high programming cost using RTL, none of the mainstream MD software packages has yet adopted FPGA for acceleration. In this paper we revisit the FPGA acceleration of MD in high-level synthesis (HLS) so as to provide affordable programming cost. Our experience with the MD acceleration demonstrates that HLS optimizations such as loop pipelining, module duplication and memory partitioning are essential to improve the performance, achieving a speedup of 9.5X compared to a 12-core CPU. More importantly, we observe that even the fully optimized HLS design can still be 2X slower than the reference RTL architecture due to the common dynamic (conditional) data flow behavior that is not yet supported by current HLS tools. To support such behavior, we further customize an array of processing elements together with a data-driven streaming network through a common RTL template, and fully automate the design flow. Our final experimental results demonstrate a 19.4X performance speedup and 39X energy efficiency for the widely used ApoA1 MD benchmark on the Convey HC1ex FPGA compared to a 12-core Intel Xeon server.
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