Parendi：千路并行 RTL 仿真
Parendi: Thousand-Way Parallel RTL Simulation
AI总结：
本文提出并行 RTL 仿真器 Parendi，通过分区、编译技术将细粒度并行映射到 Graphcore IPU，在 5888 核上实现大型设计最高 4 倍于先进 x64 多核系统的速度。
摘要：
硬件开发关键依赖于周期精确的 RTL 仿真。然而，随着芯片复杂性不断增加，由于单核性能停滞，传统的单线程仿真已变得不切实际。Parendi 是一款 RTL 仿真器，通过利用 RTL 仿真中固有的大量细粒度并行性，并将其高效映射到大规模并行的 Graphcore IPU（Intelligence Processing Unit，智能处理单元）架构上来应对这一挑战。Parendi 可扩展至 4 个 Graphcore IPU 插槽上的 5888 个核心。它使我们能够运行大型 RTL 设计，速度最高可达最强大的先进 x64 多核系统的 4 倍。为实现这一性能，我们开发了新的分区和编译技术，并仔细量化了并行 RTL 仿真的同步、通信和计算成本：本文全面分析了这些因素，并详细介绍了 Parendi 用于优化它们的策略。
英文摘要：
Hardware development critically depends on cycle-accurate RTL simulation. However, as chip complexity increases, conventional single-threaded simulation becomes impractical due to stagnant single-core performance. Parendi is an RTL simulator that addresses this challenge by exploiting the abundant fine-grained parallelism inherent in RTL simulation and efficiently mapping it onto the massively parallel Graphcore IPU (Intelligence Processing Unit) architecture. Parendi scales up to 5888 cores on 4 Graphcore IPU sockets. It allows us to run large RTL designs up to 4$\times$ faster than the most powerful state-of-the-art x64 multicore systems. To achieve this performance, we developed new partitioning and compilation techniques and carefully quantified the synchronization, communication, and computation costs of parallel RTL simulation: The paper comprehensively analyzes these factors and details the strategies that Parendi uses to optimize them.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
