arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2206.13645quant-phcs.ET
收藏

基于拓扑综合的宽量子线路优化

Wide Quantum Circuit Optimization with Topology Aware Synthesis

Mathias Weiden, Justin Kalloor, John Kubiatowicz, Ed Younis, Costin Iancu

摘要:

幺正合成是一种优化技术,可以在将量子线路映射到限制性量子比特拓扑结构的同时实现最佳的多量子比特门计数。由于合成算法在可扩展性方面受到其指数增长的运行时间和存储器需求的限制,因此应用于宽于5个量子位的电路需要将电路分割成更小的组件。在这项工作中,我们将探索减少深度(程序运行时间)和多量子位门指令计数的宽(16-100量子位)映射的量子线路优化与综合的方法。减少电路深度和门数直接影响并行量子机上的量子线路的程序性能和成功执行的可能性。我们提出了TopAS,一个拓扑感知的合成工具,内置的\emph{BQSKit}框架,前提条件量子线路映射之前。分区的子电路被优化并以平衡合成和映射算法的通常相反的需求的方式适合于稀疏量子比特子拓扑。这种技术可用于减少映射到Google和IBM稀疏量子位拓扑的宽量子线路的深度和门数。与大规模综合算法相比,TopAS在映射后专注于优化量子线路,当目标为2D网状拓扑时,深度平均减少35.2%,CNOT门数平均减少11.5%。当与传统的量子编译器使用窥视孔优化和映射算法的Qiskit或$t|ket\rangle$工具包相比,我们的方法是能够提供显着的性能改善,减少CNOT计数30.3%和深度平均38.2%。

英文摘要:

Unitary synthesis is an optimization technique that can achieve optimal multi-qubit gate counts while mapping quantum circuits to restrictive qubit topologies. Because synthesis algorithms are limited in scalability by their exponentially growing run time and memory requirements, application to circuits wider than 5 qubits requires divide-and-conquer partitioning of circuits into smaller components. In this work, we will explore methods to reduce the depth (program run time) and multi-qubit gate instruction count of wide (16-100 qubit) mapped quantum circuits optimized with synthesis. Reducing circuit depth and gate count directly impacts program performance and the likelihood of successful execution for quantum circuits on parallel quantum machines. We present TopAS, a topology aware synthesis tool built with the \emph{BQSKit} framework that preconditions quantum circuits before mapping. Partitioned subcircuits are optimized and fitted to sparse qubit subtopologies in a way that balances the often opposing demands of synthesis and mapping algorithms. This technique can be used to reduce the depth and gate count of wide quantum circuits mapped to the sparse qubit topologies of Google and IBM. Compared to large scale synthesis algorithms which focus on optimizing quantum circuits after mapping, TopAS is able to reduce depth by an average of 35.2% and CNOT gate count an average of 11.5% when targeting a 2D mesh topology. When compared with traditional quantum compilers using peephole optimization and mapping algorithms from the Qiskit or $t|ket\rangle$ toolkits, our approach is able to provide significant improvements in performance, reducing CNOT counts by 30.3% and depth by 38.2% on average.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

↑