基于半张量积的量子电路并行精确合成
Parallelizable Exact Synthesis of Quantum Circuits via Semi-Tensor Product
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中文总结 AI 辅助
针对现有量子电路精确合成方法的不足，本文基于半张量积理论，为CNOT和相位多项式电路引入并行精确合成框架，通过特定枚举和求解方式实现并行加速，在小实例上比基线快，在实际工作流程中多数情况表现更优。
中文摘要 AI 辅助
精确合成是量子编译中的有用工具，可提供小电路片段的最优替代实现，广泛用作电路重新合成优化内核。但现有方法存在编码开销、并行扩展性差和内存瓶颈问题。本文基于矩阵半张量积（STP）理论，为CNOT和相位多项式电路引入并行精确合成框架。通过枚举无向部分门拓扑并分别求解缺失门方向，实现两阶段并行，在该NP难问题上32个工作线程可实现高达12.8倍的并行加速。具体而言，将电路语义转换为规范STP公式，通过从右到左的分解过程确定可行性并去除不可行方向分配。在随机生成的合成目标上，STP在小实例上通常比基于SAT的基线快100到1000倍，在更难实例上也具竞争力。在实际电路优化工作流程中，算法在QASMBench中89%的情况优于基于SAT的方法，实现中位数加速1.91倍。
英文摘要
Exact synthesis is a key infrastructure in quantum circuit synthesis and optimization, which provides optimal implementations of small circuit shards and is widely used as a circuit re-synthesis optimization kernel. However, existing quantum exact synthesis methods suffer from encoding overhead, memory bottlenecks, and poor parallel scalability. In this work, we introduce a parallel exact synthesis framework for CNOT and phase polynomial circuits based on the semi-tensor product (STP) theory of matrices that avoids these issues. The algorithm contains two stages: it first enumerates candidate circuit topologies, and then instantiates each topology by determining the control and target qubit of its partial gates via a STP-based circuit solver. In the second stage, circuit topologies are encoded as canonical STP expressions, and the CNOT gates are synthesized through right-to-left STP matrix factorization that progressively eliminates infeasible gate decisions. In the framework, topology enumeration and the subsequent solving process are independent across different topologies, and can be naturally parallelized. Despite the NP-hardness of the problem, our algorithm yields up to $12.8\times$ parallel speedup with 32 workers, whereas the parallel speedups of existing SAT-based methods remain below $5\times$ with the same worker budget. On randomly generated synthesis targets, the proposed algorithm is typically $100$-$1000\times$ faster than the SAT-based approach on small and moderately difficult instances, and remains competitive for more difficult instances. When integrated in a real-world circuit optimization workflow, our algorithm achieves a median speedup of $3.41\times$ on the QASMBench benchmark.
