The bilateral filter (BF) is widely used in image processing because it can perform denoising while preserving edges. It has disadvantages in that it is nonlinear, and its computational complexity and hardware resources are directly proportional to its window size. Thus far, several approximation methods and hardware implementations have been proposed to solve these problems. However, processing large-scale and high-resolution images in real time under severe hardware resource constraints remains a challenge.
This paper proposes a real-time image denoising system that uses an FPGA based on the bilateral grid (BG). In the BG, a 2D image consisting of x- and y-axes is projected onto a 3D space called a "grid," which consists of axes that correlate to the x-component, y-component, and intensity value of the input image. This grid is then blurred using the Gaussian filter, and the output image is generated by interpolating the grid. Although it is possible to change the window size in the BF, it is impossible to change it on the input image in the BG. This makes it difficult to associate the BG with the BF and to obtain the property of suppressing the increase in hardware resources when the window radius is enlarged.
This study demonstrates that a BG with a variable-sized window can be realized by introducing the window radius parameter wherein the window radius on the grid is always 1. We then implement this BG on an FPGA in a fully pipelined manner. Further, we verify that our design suppresses the increase in hardware resources even when the window size is enlarged and outperforms the existing designs in terms of computation speed and hardware resources.
RidgeWalker: Perfectly Pipelined Graph Random Walks on FPGAs
National University of Singapore（新加坡国立大学）；The Hong Kong University of Science and Technology (Guangzhou)（香港科技大学（广州））；University of Toronto（多伦多大学）；ByteDance（字节跳动）
HG-PIPE: Vision Transformer Acceleration with Hybrid-Grained Pipeline
School of Integrated Circuits, Peking University（北京大学集成电路学院）；Institute for Artificial Intelligence, Peking University（北京大学人工智能研究院）；School of Software and Microelectronics, Peking University（北京大学软件与微电子学院）；Beijing Advanced Innovation Center for Integrated Circuits（北京集成电路高精尖创新中心）
本文提出 HG-PIPE 流水线 FPGA 加速器，通过混合粒度架构、数据流与并行耦合及 LUT 近似消除气泡并降低资源开销，显著提升 ViT 吞吐与能效。
VQ4SNN: Vector Quantization for Memory-Efficient FPGA Spiking Neural Networks
Integrated Circuits Lab, Electrical and Computer Engineering, Democritus University of Thrace (DUTH), Greece（德米特里乌斯特拉基亚大学集成电路实验室，电气与计算机工程，特拉基亚大学（DUTH），希腊）
Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform
Beihang University（北京航空航天大学）；Xidian University（西安电子科技大学）；Beijing Real Imaging Medical Technology Co., Ltd.（北京真实影像医疗科技有限公司）；The Chinese University of Hong Kong（香港中文大学）
Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
Nara Institute of Science and Technology（奈良先端科学技术大学院大学）；University of Information Technology（信息工程大学）；Vietnam National University（越南国立大学）；Le Quy Don Technical University（黎贵敦技术大学）
