自适应混合FFT：一种面向大尺寸处理中基-$2^k$ FFT的新型流水线与基于存储器架构
Adaptive Hybrid FFT: A Novel Pipeline and Memory-Based Architecture for Radix-$2^k$ FFT in Large Size Processing
AI总结：
本文提出一种自适应混合FFT处理器，结合流水线与基于存储器架构优势，通过基-$2^k$ MDC单元、无冲突访存方案和位维置换实现大尺寸高性能处理，并在FPGA上验证其优于传统方案。
摘要：
在数字信号处理领域，快速傅里叶变换（FFT）是一种基础算法，其处理器要么采用流水线架构实现，该架构以高吞吐量应用著称但硬件利用率较低，要么采用基于存储器的架构，该架构面向面积受限场景设计但无法满足严格的吞吐量要求。因此，我们提出一种自适应混合FFT，它同时利用流水线架构和基于存储器架构的优势。本文提出一种自适应混合FFT处理器，结合了两种架构的优点，并具有以下特征。第一，开发了一组基-$2^k$多路径延迟换向器（MDC）单元，以支持高性能大尺寸处理。第二，制定了一种无冲突存储器访问方案，以确保连续数据流而无数据争用。第三，我们证明了存在一系列位维置换用于重排输入数据，满足可变长度、高基数和任意并行度水平的广义约束，从而实现广泛的自适应性。此外，所提出的FFT处理器已在现场可编程门阵列（FPGA）上实现。结果表明，所提出的工作优于传统的基于存储器的FFT处理器，所需计算周期更少。它实现了比流水线FFT架构更高的硬件利用率，使其适用于高要求应用。
英文摘要：
In the field of digital signal processing, the fast Fourier transform (FFT) is a fundamental algorithm, with its processors being implemented using either the pipelined architecture, well-known for high-throughput applications but weak in hardware utilization, or the memory-based architecture, designed for area-constrained scenarios but failing to meet stringent throughput requirements. Therefore, we propose an adaptive hybrid FFT, which leverages the strengths of both pipelined and memory-based architectures. In this paper, we propose an adaptive hybrid FFT processor that combines the advantages of both architectures, and it has the following features. First, a set of radix-$2^k$ multi-path delay commutators (MDC) units are developed to support high-performance large-size processing. Second, a conflict-free memory access scheme is formulated to ensure a continuous data flow without data contention. Third, We demonstrate the existence of a series of bit-dimension permutations for reordering input data, satisfying the generalized constraints of variable-length, high-radix, and any level of parallelism for wide adaptivity. Furthermore, the proposed FFT processor has been implemented on a field-programmable gate array (FPGA). As a result, the proposed work outperforms conventional memory-based FFT processors by requiring fewer computation cycles. It achieves higher hardware utilization than pipelined FFT architectures, making it suitable for highly demanding applications.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
