流水线并行FFT体系结构
Pipelined Parallel FFT Architecture
摘要：
本文提出了一种能产生逆输出序列的流水线快速傅里叶变换（FFT）处理器的优化高效VLSI结构。提出了一种用于FFT计算的基2多径延迟结构。FFT在硬件中的实现是非常关键的，因为对于FFT的计算，蝶形运算的数量，即乘法器的数量，由于硬件的增加，意味着硬件的间接成本自动增加。乘法器的运算速度也很慢，这就是为什么它限制了架构的运算速度。本文提出了FFT算法的优化VLSI实现方法。这里的架构是流水线优化，并提高操作速度。此外，为了提高操作速度，使用2级并行处理。
英文摘要：
In this paper, an optimized efficient VLSI architecture of a pipeline Fast Fourier transform (FFT) processor capable of producing the reverse output order sequence is presented. Paper presents Radix-2 multipath delay architecture for FFT calculation. The implementation of FFT in hardware is very critical because for calculation of FFT number of butterfly operations i.e. number of multipliers requires due to which hardware gets increased means indirectly cost of hardware is automatically gets increased. Also multiplier operations are slow that's why it limits the speed of operation of architecture. The optimized VLSI implementation of FFT algorithm is presented in this paper. Here architecture is pipelined to optimize it and to increase the speed of operation. Also to increase the speed of operation 2 levels parallel processing is used.
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