FPGA流水线数字切片无乘法器基2的2次方DIF SDF蝶形傅里叶变换结构的实现
FPGA Implementation of pipeline Digit-Slicing Multiplier-Less Radix 2 power of 2 DIF SDF Butterfly for Fourier Transform Structure
摘要：
对无线通信的需求已经将通信系统推向高性能。然而，影响通信能力的主要瓶颈是快速傅里叶变换（FFT），它是大多数调制器的核心。提出了一种基于FPGA的流水线数字切片无乘法器基22 DIF（频率抽取）SDF（单路延迟反馈）蝶形FFT结构的实现方法。为了降低蝶形乘法器的计算复杂度，在流水线基22 DIF SDF FFT结构的关键路径上采用了数字切片无乘法器技术。所提出的设计集中在芯片实现的速度和有源硅面积之间的权衡。乘法器输入数据被分割成四个块，每个块具有四位，以并行方式同时处理。利用MATLAB软件对新结构进行了研究和仿真。在Xilinx ISE环境下推导了描述FFT Butterfly功能的Verilog HDL代码，并下载到Virtex II FPGA板上。因此，Virtex-II FG 456 Proto板被用于在真实硬件上实现和测试该设计。因此，根据研究结果，综合报告表明，最大时钟频率为555.75 MHz，总等效门数为32，146，与基22 DIF SDF FFT蝶形相比，有了显著的改进。与最高时钟频率仅为200.102 MHz的传统蝶形结构设计和最高时钟频率仅为221.140 MHz的传统乘法器相比，该系统具有更好的性能。
英文摘要：
The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This paper presents FPGA implementation of pipeline digit-slicing multiplier-less radix 22 DIF (Decimation In Frequency) SDF (single path delay feedback) butterfly for FFT structure. The approach is taken, in order to reduce computation complexity in butterfly multiplier, the digit-slicing multiplier-less technique was utilized in the critical path of pipeline Radix-22 DIF SDF FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The multiplier input data was sliced into four blocks each one with four bits to process at the same time in parallel. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 555.75 MHz with the total equivalent gate count of 32,146 is a marked and significant improvement over Radix 22 DIF SDF FFT butterfly. In comparison with the conventional butterfly architecture design which can only run at a maximum clock frequency of 200.102 MHz and the conventional multiplier can only run at a maximum clock frequency of 221.140 MHz, the proposed system exhibits better results.
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