arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2109.05229cond-mat.mes-hallphysics.app-ph
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n位数据并行自旋波逻辑门

n-bit Data Parallel Spin Wave Logic Gate

Abdulqader Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui

摘要:

由于它们的性质,在同一波导中产生的自旋波(SW),但具有不同的频率,可以共存,同时选择性地只与它们自己的物种相互作用。频率间干扰的不存在隔离了在具有不同频率的SW中编码的输入数据集,并且为同时数据并行的基于SW的处理创建了前提,而没有硬件复制或延迟开销。在本文中,我们利用这种SW属性,通过引入一种新的计算范式,它允许在相同的基本SW逻辑门的n位输入数据向量的并行处理。随后,为了证明所提出的概念,我们提出了8位并行3输入多数门实现,并通过面向对象的微磁框架(OOMMF)模拟验证。为了评估我们的建议的潜在好处,我们比较了8位数据并行门与等效标量SW门为基础的实现。我们的评估表明,8位数据3输入多数门的实现需要4.16倍的面积小于标量SW门为基础的等效对应,同时保持相同的延迟和能耗数字。

英文摘要:

Due to their very nature, Spin Waves (SWs) created in the same waveguide, but with different frequencies, can coexist while selectively interacting with their own species only. The absence of inter-frequency interferences isolates input data sets encoded in SWs with different frequencies and creates the premises for simultaneous data parallel SW based processing without hardware replication or delay overhead. In this paper we leverage this SW property by introducing a novel computation paradigm, which allows for the parallel processing of n-bit input data vectors on the same basic SW based logic gate. Subsequently, to demonstrate the proposed concept, we present 8-bit parallel 3-input Majority gate implementation and validate it by means of Object Oriented MicroMagnetic Framework (OOMMF) simulations. To evaluate the potential benefit of our proposal we compare the 8-bit data parallel gate with equivalent scalar SW gate based implementation. Our evaluation indicates that 8-bit data 3-input Majority gate implementation requires 4.16x less area than the scalar SW gate based equivalent counterpart while preserving the same delay and energy consumption figures.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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