Koios：用于FPGA架构和CAD研究的深度学习基准套件
Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
摘要：
随着深度学习（DL）在许多应用中的流行，研究人员正在研究优化FPGA架构和CAD的不同方法，以在基于DL的工作负载上实现更好的结果质量（QoR）。在这个优化过程中，基准电路是一个重要的组成部分;在一组基准上实现的QoR是架构和CAD设计选择的主要驱动力。然而，目前的学术基准套件是不够的，因为它们没有捕获任何设计从DL域。这项工作提出了一套新的DL加速基准电路的FPGA架构和CAD研究，称为Koios。这套19个电路涵盖了各种各样的加速神经网络，设计尺寸，实现风格，抽象层次和数值精度。与现有的开源基准测试相比，这些设计更大，数据更并行，更异构，更深入的流水线，并利用更多的FPGA架构功能。这使研究人员能够针对此类工作负载确定架构效率低下的问题，并在更现实的基准上优化CAD工具，这些基准以不同的方式强调CAD算法。在本文中，我们描述了我们的基准测试套件的设计，目前的结果，通过Verilog的路由（VTR）流使用最新的FPGA架构模型运行它们，并确定从所产生的指标的关键见解。与广泛使用的VTR套件相比，我们的基准测试平均具有3.7倍的网表原语，1.8倍和4.7倍的DSP和BRAM密度，以及1.7倍的频率和1.9倍的近关键路线。最后，我们提出了两个示例案例研究，展示了如何使用我们的新基准测试套件进行DL优化FPGA的架构探索。
英文摘要：
With the prevalence of deep learning (DL) in many applications, researchers are investigating different ways of optimizing FPGA architecture and CAD to achieve better quality-of-results (QoR) on DL-based workloads. In this optimization process, benchmark circuits are an essential component; the QoR achieved on a set of benchmarks is the main driver for architecture and CAD design choices. However, current academic benchmark suites are inadequate, as they do not capture any designs from the DL domain. This work presents a new suite of DL acceleration benchmark circuits for FPGA architecture and CAD research, called Koios. This suite of 19 circuits covers a wide variety of accelerated neural networks, design sizes, implementation styles, abstraction levels, and numerical precisions. These designs are larger, more data parallel, more heterogeneous, more deeply pipelined, and utilize more FPGA architectural features compared to existing open-source benchmarks. This enables researchers to pin-point architectural inefficiencies for this class of workloads and optimize CAD tools on more realistic benchmarks that stress the CAD algorithms in different ways. In this paper, we describe the designs in our benchmark suite, present results of running them through the Verilog-to-Routing (VTR) flow using a recent FPGA architecture model, and identify key insights from the resulting metrics. On average, our benchmarks have 3.7x more netlist primitives, 1.8x and 4.7x higher DSP and BRAM densities, and 1.7x higher frequency with 1.9x more near-critical paths compared to the widely-used VTR suite. Finally, we present two example case studies showing how architectural exploration for DL-optimized FPGAs can be performed using our new benchmark suite.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
