少有人走的路：面向FPGA的感知拥塞片上网络布局与分组路由
The Road Less Traveled: Congestion-Aware NoC Placement and Packet Routing for FPGAs
浏览论文内容
中文总结 AI 辅助
本研究针对FPGA的片上网络拥塞问题，在开源CAD工具VPR中融入拥塞建模、转弯模型路由、SAT路由建模及强化学习智能体优化，显著降低了NoC拥塞并缩短了线长。
中文摘要 AI 辅助
为助力FPGA适配日益庞大复杂的设计，近期FPGA架构已集成片上网络（NoC）。NoC可在芯片内远距离传输高带宽数据，且无需占用稀缺的低延迟长布线线段。尽管NoC增强型FPGA有助于系统集成与设计复用，但也因引入新约束和指标，使FPGA计算机辅助设计（CAD）流程更为复杂。布局与布线需优化NoC的延迟、带宽利用率等指标，避免链路过度订阅（即拥塞），同时优化连接NoC路由器的设计模块的可编程布线资源使用。本研究开发多种新方法以减少NoC拥塞，同时最小化对其他设计指标的影响。首先，我们将NoC链路拥塞代价融入开源CAD流程VPR（versatile place & route）的布局引擎。其次，我们将转弯模型（turn model）NoC路由算法集成到布局引擎，以利用路径多样性进一步减少拥塞。在29个基准测试集的平均结果中，结合布局拥塞建模与转弯模型分组路由可将NoC拥塞降低90.7%，代价是总带宽需求增加4%。当增强后的布局引擎与NoC路由无法完全解决拥塞时，我们将NoC路由建模为布尔可满足性（SAT）问题，该方法带来显著额外改进；与基线布局相比，组合算法可将拥塞降低95.1%。最后，我们通过引入感知NoC的移动类型，增强VPR布局引擎中的强化学习（RL）智能体，在大量使用NoC的设计上，线长缩短8.8%。
英文摘要
To help scale to ever-larger and more complex designs, recent FPGA architectures now integrate network-on-chips (NoCs). NoCs help transfer high-bandwidth data over long distances within the chip without using scarce low-delay long routing wire segments. While NoC-enhanced FPGAs aid system integration and design reuse, they also complicate FPGA computer-aided design (CAD) flows by introducing new constraints and metrics. Placement and routing need to optimize NoC metrics like latency and bandwidth utilization and avoid link oversubscription (congestion), while simultaneously optimizing the programmable routing resource usage of the design modules attached to NoC routers. In this work, we develop several new approaches to reduce NoC congestion while minimizing the impact on other design metrics. First, we incorporate a NoC link congestion cost into the placement engine of the open-source CAD flow, versatile place & route (VPR). Second, we integrate turn model NoC routing algorithms into the placement engine to leverage path diversity to further reduce congestion. On average over a suite of 29 benchmarks, combining placement congestion modeling with turn model packet routing reduces NoC congestion by 90.7% at the cost of increasing aggregate bandwidth demand by 4%. In cases where the enhanced placement engine and NoC routing fail to fully resolve congestion, we formulate NoC routing as a Boolean satisfiability (SAT) problem. This approach yields significant additional improvements; the combined algorithm reduces congestion by 95.1% compared to the baseline placement. Finally, we enhance the reinforcement learning (RL) agent in VPR's placement engine by introducing a NoC-aware move type, resulting in an 8.8% reduction in wirelength on designs that make extensive use of the NoC.
