面向多芯片FPGA的互连感知逻辑综合
Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs
AI总结：
本文提出一种互连感知逻辑综合方法，通过重构LUT级网表减少超长线数量，提升多芯片FPGA的物理设计灵活性。
摘要：
多芯片FPGA使器件规模突破光刻限制，但跨芯片互连开销严重。超长线（SLLs）导致高延迟并消耗稀缺互连资源，常主导关键路径。本文提出一种互连感知逻辑综合方法，通过芯片划分信息应用逻辑重置换，简化局部电路结构并消除SLLs。在设计流程早期减少SLLs数量，缓解互连资源压力并提升物理设计灵活性。通过整合逻辑综合、布局和放置构建多芯片FPGA工具流。实验结果表明，相比现有框架，该方法在2芯片FPGA上减少SLLs达24.8%，3芯片FPGA达27.38%。在MCNC基准上，工具流实现平均SLLs减少1.65%并保持布局质量。在Koios基准上，尽管可移除SLLs较少，多个设计仍显示显著的跨芯片边沿减少。结果证实，在逻辑层面减少跨芯片连接是多芯片FPGA的有效方法。
英文摘要：
Multi-die FPGAs enable device scaling beyond reticle limits but introduce severe interconnect overhead across die boundaries. Inter-die connections, commonly referred to as super-long lines (SLLs), incur high delay and consume scarce interposer interconnect resources, often dominating critical paths and complicating physical design. To address this, this work proposes an interconnect-aware logic resynthesis method that restructures the LUT-level netlist to reduce the number of SLLs. The resynthesis engine uses die partitioning information to apply logic resubstitutions, which simplifies local circuit structures and eliminates SLLs. By reducing the number of SLLs early in the design flow, prior to physical implementation, the proposed method shortens critical paths, alleviates pressure on scarce interposer interconnect resources, and improves overall physical design flexibility. We further build a tool flow for multi-die FPGAs by integrating the proposed resynthesis method with packing and placement. Experimental results on the EPFL benchmarks show that, compared with a state-of-the-art framework, the proposed method reduces the number of SLLs by up to 24.8% for a 2-die FPGA and up to 27.38% for a 3-die FPGA. On MCNC benchmarks, our tool flow achieves an average SLL reduction of 1.65% while preserving placement quality. On Koios benchmarks, where fewer removable SLLs exist, several designs still exhibit considerable inter-die edge reductions. Overall, the results confirm that reducing inter-die connections at the logic level is an effective approach for multi-die FPGAs.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
