Rect3D：三维集成电路直角布线规划的统一定析框架

中文摘要 AI 辅助

三维集成电路通过减少全局互连成本，为现代超大规模集成电路设计带来了显著的性能提升。然而，传统的三维布线规划方法将问题分解为独立的层间划分和层内布线规划两个阶段，这可能会限制设计优化空间并削弱潜在收益。尽管直接在三维空间中进行建模和优化可以缓解这一限制，但高计算复杂度阻碍了算法效率。为应对这些挑战，我们提出了Rect3D，一个解析式三维直角布线规划框架，它将概率性层间块分配整合到一个统一的连续优化模型中。该框架结合了用于拓扑感知初始化的图拉普拉斯初始化、用于联合层分配和几何细化的可扩展梯度下降全局优化过程，以及一种基于三维网格的合法化方法，以生成连通的直角布局。在GSRC基准测试上，与代表性的最先进三维布线规划基线相比，Rect3D将线长减少了最多83.6%，运行时间减少了最多15.98倍。此外，在六个额外的先划分后布线直角基线中，它始终实现了最低的线长，展示了在统一三维优化流程中保留层分配和层内几何的优势。

英文摘要

3D-ICs offer significant performance improvements for modern VLSI designs by reducing global interconnect cost. However, conventional 3D floorplanning methods decompose the problem into separate inter-die partitioning and intra-die floorplanning stages, which can restrict the design optimization space and limit the potential gains. Although directly modeling and optimizing in 3D space can mitigate this limitation, the high computational complexity hinders algorithmic efficiency. To address these challenges, we propose \textsc{Rect3D}, an analytical 3D rectilinear floorplanning framework that integrates probabilistic inter-die block assignment into a unified continuous optimization model. The framework combines graph Laplacian initialization for topology-aware seeding, a scalable gradient-based global optimization procedure for joint die assignment and geometric refinement, and a 3D grid-based legalization method for generating connected rectilinear layouts. On GSRC benchmarks, \textsc{Rect3D} reduces wirelength by up to 83.6\% and runtime by up to 15.98$\times$ compared with representative state-of-the-art 3D floorplanning baselines. It also consistently achieves the lowest wirelength among six additional partition-first rectilinear baselines, showing the advantage of preserving die assignment and in-die geometry in a unified 3D optimization flow.

发表机构

• The Chinese University of Hong Kong（香港中文大学）
• Eastern Institute of Technology, Ningbo（宁波东方理工学院）

机构由 AI 辅助整理，请以论文原文为准。

补充信息

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12pages, 16 figures