FPGA在130 nm CMOS中具有改进的可重复性和稳健性，具有开源CAD靶向性
FPGA with Improved Routability and Robustness in 130nm CMOS with Open-Source CAD Targetability
摘要：
本文概述了一种FPGA的VLSI设计方法，用于实现一个功能齐全的FPGA芯片在130纳米CMOS与改进的可布线性和存储器的鲁棒性。Verilog-to-Routing CAD工具使建筑设计空间探索和综合能力成为可能。该工具的功能已扩展到支持比特流生成和部署。为了验证架构和比特流实现，创建了FPGA的Chisel（用嵌入式Scala语言构建硬件）模型，以在原理图设计之前快速验证器件的微架构细节。使用定制载板和配置工具来验证FPGA在各种资源利用率和时钟频率下的正确操作特性。
英文摘要：
This paper outlines an FPGA VLSI design methodology that was used to realize a fully functioning FPGA chip in 130nm CMOS with improved routability and memory robustness. The architectural design space exploration and synthesis capability were enabled by the Verilog-to-Routing CAD tool. The capabilities of this tool were extended to enable bitstream generation and deployment. To validate the architecture and bitstream implementation, a Chisel (Constructing Hardware in the Embedded Scala Language) model of the FPGA was created to rapidly verify the microarchitectural details of the device prior to schematic design. A custom carrier board and configuration tool were used to verify correct operational characteristics of the FPGA over various resource utilizations and clock frequencies.
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