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arXiv 2102.06117quant-phcs.PF
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脉冲工程设计的受控-V门及其在超导量子器件上的应用

Pulse-engineered Controlled-V gate and its applications on superconducting quantum device

Takahiko Satoh, Shun Oomura, Michihiko Sugawara, Naoki Yamamoto

AI总结:

本文提出利用OpenPulse设计套件在IBM超导量子器件上实现脉冲工程设计的CV门,使其门时间减半且相比CX实现减少65.5%,并基于Cartan分解理论刻画了仅需两三个CV门的双量子比特门集合,实验证明该方法能缩短门时间、提升保真度,从而优化量子算法精度。

摘要:

在本文中,我们证明,通过为IBM超导量子器件采用OpenPulse设计套件,受控-V门(CV门)可以在约为受控-X门(CX或CNOT门)一半的门时间内实现,因此与基于CX的CV实现相比,门时间减少了65.5%。然后,基于Cartan分解理论,我们刻画了仅用两个或三个CV门实现的所有双量子比特门集合;使用脉冲工程设计的CV门使我们能够以更短的门时间和可能更好的门保真度来实现这些门(相比基于CX的实现),正如在两个实例中所实际演示的那样。此外,我们展示了线性耦合的三量子比特Toffoli门的改进,通过使用脉冲工程设计的CV门来实现它,在门时间和平均输出态保真度上均有提升。这些结果意味着我们的CV门实现技术的重要性,作为基门集设计的一个额外选项,它可能缩短整体计算时间,从而提高在真实器件上执行的若干量子算法的精度。

英文摘要:

In this paper, we demonstrate that, by employing OpenPulse design kit for IBM superconducting quantum devices, the controlled-V gate (CV gate) can be implemented in about half the gate time to the controlled-X (CX or CNOT gate) and consequently 65.5\% reduced gate time compared to the CX-based implementation of CV. Then, based on the theory of Cartan decomposition, we characterize the set of all two-qubit gates implemented with only two or three CV gates; using pulse-engineered CV gates enables us to implement these gates with shorter gate time and possibly better gate fidelity than the CX-based one, as actually demonstrated in two examples. Moreover, we showcase the improvement of linearly-coupled three-qubit Toffoli gate, by implementing it with the pulse-engineered CV gate, both in gate time and the averaged output-state fidelity. These results imply the importance of our CV gate implementation technique, which, as an additional option for the basis gate set design, may shorten the overall computation time and consequently improve the precision of several quantum algorithms executed on a real device.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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