A Comparative Study between HLS and HDL on SoC for Image Processing Applications

从 GSA 到 HDL：迈向动态调度电路的原则化生成

GSA to HDL: Towards principled generation of dynamically scheduled circuits

针对动态调度 HLS 因保守假设导致性能次优的问题，提出 h-GSA 抽象及从 GSA 到硬件电路的 lowering 流程，并与 Dynamatic 比较验证性能提升潜力。

通过高层次综合加速基于FPGA的Wi-Fi收发机设计与原型验证

Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis

本文提出利用高层次综合（HLS）设计OFDM基带处理模块并集成至HDL，在不到一个月内实现性能开销极小的FPGA Wi-Fi收发机，验证了HLS在加速SDR设计与原型开发中的可行性与优势。

DP-HLS：一种用于加速生物信息学中动态规划算法的高层次综合框架

DP-HLS: A High-Level Synthesis Framework for Accelerating Dynamic Programming Algorithms in Bioinformatics

本文提出DP-HLS框架，基于高层次综合简化生物信息学中动态规划算法的硬件开发，将开发时间从数月缩短至数天，实现15个内核，吞吐量较GPU/CPU提升1.3-32倍，性能差距在7.7%-16.8%以内。

On The Design of a Light-weight FPGA Programming Framework for Graph Applications

FPGA accelerators designed for graph processing are gaining popularity. Domain Specific Language (DSL) frameworks for graph processing can reduce the programming complexity and development cost of algorithm design. However, accelerator-specific development requires certain technical expertise and significant effort to devise, implement, and validate the system. For most algorithm designers, the expensive cost for hardware programming experience makes FPGA accelerators either unavailable or uneconomic. Although general-purpose High-Level Synthesis (HLS) tools help to map high-level language to …

HLS-Eval：用于评估大语言模型在高层次综合设计任务中表现的基准与框架

HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks

HLS-Eval是首个评估LLM在高层次综合设计任务中的基准与框架，包含94个设计，支持代码生成与编辑，并提供自动化并行评估工具，已在Vitis HLS上建立基线。

SyntheticHLS：利用大语言模型构建多样化综合高级综合数据集

SyntheticHLS: Building Diverse Synthetic High-Level Synthesis Datasets using LLMs

针对HLS数据集稀缺且多样性不足的问题，提出SyntheticHLS框架，利用LLM的迭代反馈引导变异和定量指标生成多样化合成数据集，经交叉验证表明其训练语料库泛化性最佳。