A portable and Linux capable RISC-V computer system in Verilog HDL

Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator

Timing-abstract and transaction-level design using TL-Verilog have shown significant productivity gains for logic design. In this work, we explored the natural extension of transaction-level design methodology into formal verification. WARP-V is a CPU core generator written in TL-Verilog. Our primary verification vehicle for WARP-V was a formal verification framework for RISC-V, called riscv-formal. The timing-abstract and transaction-level logic modeling techniques of TL-Verilog greatly simplified the task of creating a harness connecting the WARP-V model to the verification interface of risc…

HaVen：与 HDL 工程师对齐的、用于 Verilog 代码生成的幻觉缓解型 LLM

HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers

本文提出 HaVen 框架，通过幻觉分类、CoT 符号转译和面向 HDL 工程实践的数据增强，提升 LLM 的 Verilog 生成正确性，并在 VerilogEval 与 RTLLM 上超过现有方法。

RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions

In this paper, we propose a high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions targeting on FPGA. The compressed instruction extension in RISC-V can reduce the program size by about 25%. But it needs a complicated logic for the instruction fetch unit and has a significant impact on performance. We propose an instruction fetch unit that supports the compressed instructions while exhibiting high performance. Furthermore, we propose a RISC-V soft processor using this unit. We implement this proposed processor in Verilog HDL and verify the be…

vlang: Mapping Verilog Netlists to Modern Technologies

Portability of hardware designs between Programmable Logic Devices (PLD) can be accomplished through the use of device-agnostic hardware description languages (HDL) such as Verilog or VHDL. Hardware designers can use HDLs to migrate hardware designs between devices and explore performance, area and power tradeoffs, as well as, port designs to an alternative device. However, if design files are corrupt or missing, the portability of the design is lost. While reverse engineering efforts may be able to recover an HDL-netlist of the original design, HDL-netlists use device-specific primitives, res…

RVCoreP : An optimized RISC-V soft processor of five-stage pipelining

RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. The processor applies three effective optimization methods to improve the operating frequency. These methods are instruction fetch unit optimization inclu…

HiVeGen——面向可扩展芯片设计的基于层次化LLM的Verilog生成

HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design

针对LLM生成硬件代码缺乏层次结构导致幻觉的问题，提出HiVeGen层次化Verilog生成框架，通过子模块分解、自动DSE、权重检索和实时交互，提升复杂设计生成质量。