AI 中文总结
本研究开发基于忆阻器的储备池计算框架用于流水线处理器分支预测，经Dhrystone基准测试展现高预测准确率，但适应速度较TAGE预测器慢15倍，需进一步优化。
AI 中文摘要
本项目旨在开发一种新型储备池计算（RC）实现框架，目标是实现高速运行并与CMOS数字逻辑集成，针对的目标工作负载是多级流水线中央处理器（CPU）核心的分支预测（BP）。为此，结合工作负载需求开发了一种新型基于忆阻器的RC设计框架，随后采用行业标准建模语言System Verilog（SV）和Verilog-AMS（VAMS）在仿真中实现该框架。开发的RC设计框架在用于分支预测的进一步基准测试前，已通过基本序列检测任务验证。该RC框架采用Dhrystone性能基准进行测试，针对RISC-V RV64GC指令集架构（ISA）。测试表明，RC在BP应用中展现出巨大潜力，能够达到令人印象深刻的整体预测准确率；但也显示该RC设计框架需进一步优化，以解决所提RC系统适应性不足的问题。与当前最先进的TAGE预测器对比显示，所提RC设计框架对分支行为变化的适应速度慢15倍。
英文摘要
This project aimed to develop a novel reservoir compute (RC) implementation framework targeting high-speed operation and integration with CMOS digital logic. With the target workload of branch prediction (BP) for multistage pipelined central pro-cessing unit (CPU) cores. For this, a novel memristor based RC design framework was developed within the context of the workload requirements. This was then implemented in simulation using industry standard modelling languages of System Verilog (SV) and Verilog-AMS (VAMS).The developed RC design framework was subsequently verified using a basic sequence detection task before further benchmarking for its effectiveness at BP. The developed RC framework was tested using the Dhrystone performance benchmark, while targeting the RISC-V RV64GC instruction set architecture (ISA). Conducted testing demonstrates that RC shows great promise for ap-plication to BP and is capable of achieving impressive overall prediction accuracy. However, testing also shows that further refinement of the developed RC design framework is necessary to address shortfalls in the adaptability of the proposed RC system. As comparison against the state of the art TAGE predictor showed the proposed RC design framework to be 15x slower to adapt to changes in branching behaviour.
Comments53 pages, 61 figures, Master of Engineering final project report, awarded Peter John Award
