HiVeGen——面向可扩展芯片设计的基于层次化LLM的Verilog生成
HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design
AI总结：
针对LLM生成硬件代码缺乏层次结构导致幻觉的问题，提出HiVeGen层次化Verilog生成框架，通过子模块分解、自动DSE、权重检索和实时交互，提升复杂设计生成质量。
摘要：
随着大型语言模型（LLMs）近期在代码生成方面展现出令人印象深刻的能力，将其能力扩展到硬件描述语言（HDL）具有广阔前景。然而，LLMs倾向于生成单一的HDL代码块，而非硬件设计的层次化结构，这会导致幻觉现象，尤其是在领域特定加速器（DSAs）等复杂设计中。为解决此问题，我们提出HiVeGen，一种基于层次化LLM的Verilog生成框架，该框架将生成任务分解为LLM可管理的层次化子模块。HiVeGen进一步利用此类层次化结构的优势，通过将自动设计空间探索（DSE）集成到层次感知的提示生成中，引入基于权重的检索以增强代码复用，并实现实时人机交互以降低纠错成本，从而显著提升生成设计的质量。
英文摘要：
With Large Language Models (LLMs) recently demonstrating impressive proficiency in code generation, it is promising to extend their abilities to Hardware Description Language (HDL). However, LLMs tend to generate single HDL code blocks rather than hierarchical structures for hardware designs, leading to hallucinations, particularly in complex designs like Domain-Specific Accelerators (DSAs). To address this, we propose HiVeGen, a hierarchical LLM-based Verilog generation framework that decomposes generation tasks into LLM-manageable hierarchical submodules. HiVeGen further harnesses the advantages of such hierarchical structures by integrating automatic Design Space Exploration (DSE) into hierarchy-aware prompt generation, introducing weight-based retrieval to enhance code reuse, and enabling real-time human-computer interaction to lower error-correction cost, significantly improving the quality of generated designs.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
