DP-HLS：一种用于加速生物信息学中动态规划算法的高层次综合框架
DP-HLS: A High-Level Synthesis Framework for Accelerating Dynamic Programming Algorithms in Bioinformatics
AI总结：
本文提出DP-HLS框架，基于高层次综合简化生物信息学中动态规划算法的硬件开发，将开发时间从数月缩短至数天，实现15个内核，吞吐量较GPU/CPU提升1.3-32倍，性能差距在7.7%-16.8%以内。
摘要：
基于动态规划（DP）的算法是众多生物信息学流程中必不可少且计算密集的部分，这些算法通常涉及基于递归公式填充二维得分矩阵，随后可选地执行回溯步骤以获得最优比对路径。DP算法广泛应用于广泛的生物信息学任务，包括读段组装、同源搜索、基因注释、碱基识别和系统发育推断。迄今为止，专用硬件如ASIC和FPGA已为这些算法提供了巨大的加速。然而，这些解决方案通常代表DP算法空间中的单一设计点，并且通常需要使用低级硬件描述语言（HDL）花费数月的人工努力来实现。本文介绍了DP-HLS，一种基于高层次综合（HLS）的新型框架，它简化并加速了在硬件中开发广泛的生物信息学相关DP算法的过程。DP-HLS具有易于使用的模板，集成了HLS指令，无需硬件设计知识即可实现高效的硬件解决方案。根据我们的经验，DP-HLS显著减少了新内核的开发时间（从数月缩短至数天），并生成了与开源手写HDL实现相比资源利用率相当的设计，性能差距在7.7%-16.8%以内。DP-HLS兼容AWS EC2 F1 FPGA实例。为了展示DP-HLS框架的多功能性，我们实现了15个不同的DP内核，相对于最先进的GPU和CPU基线实现了1.3-32倍的吞吐量提升，并为其中几个内核提供了首个开源FPGA实现。DP-HLS代码库在MIT许可下免费提供，其详细维基可供新用户参考。
英文摘要：
Dynamic programming (DP) based algorithms are essential yet compute-intensive parts of numerous bioinformatics pipelines, which typically involve populating a 2-D scoring matrix based on a recursive formula, optionally followed by a traceback step to get the optimal alignment path. DP algorithms are used in a wide spectrum of bioinformatics tasks, including read assembly, homology search, gene annotation, basecalling, and phylogenetic inference. So far, specialized hardware like ASICs and FPGAs have provided massive speedup for these algorithms. However, these solutions usually represent a single design point in the DP algorithmic space and typically require months of manual effort to implement using low-level hardware description languages (HDLs). This paper introduces DP-HLS, a novel framework based on High-Level Synthesis (HLS) that simplifies and accelerates the development of a broad set of bioinformatically relevant DP algorithms in hardware. DP-HLS features an easy-to-use template with integrated HLS directives, enabling efficient hardware solutions without requiring hardware design knowledge. In our experience, DP-HLS significantly reduced the development time of new kernels (months to days) and produced designs with comparable resource utilization to open-source hand-coded HDL-based implementations and performance within 7.7-16.8% margin. DP-HLS is compatible with AWS EC2 F1 FPGA instances. To demonstrate the versatility of the DP-HLS framework, we implemented 15 diverse DP kernels, achieving 1.3-32x improved throughput over state-of-the-art GPU and CPU baselines and providing the first open-source FPGA implementation for several of them. The DP-HLS codebase is available freely under the MIT license and its detailed wiki is available to assist new users.
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