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arXiv 2009.07091cs.CRcs.AR
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基于格的NIST PQC算法的系统研究：从参考实现到硬件加速器

A Systematic Study of Lattice-based NIST PQC Algorithms: from Reference Implementations to Hardware Accelerators

Malik Imran, Zain Ul Abideen, Samuel Pagliarini

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38 pages and 8 figures
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摘要：

可以预见，当前部署的公钥密码学算法的安全性容易受到量子计算机攻击。因此，存在开发后量子密码学（PQC）算法的团体努力，即，能抵抗量子攻击的算法在这项工作中，我们已经调查了如何从NIST PQC标准化竞争票价格为基础的候选算法时，被认为是硬件加速器。为了实现这一目标，我们评估了所选算法的参考实现，目的是确定它们的基本构建块是什么。我们假设硬件加速器将在专用集成电路（ASIC）中实现，并且我们实验中的目标技术是商业65 nm节点。为了估计每个算法的特性，我们评估了它们的内存需求，乘法器的使用，以及每个算法如何使用哈希函数。此外，对于这些构建块，我们收集了12个候选算法的面积和功率数据。对于内存，我们使用商业内存编译器。对于逻辑，我们使用标准单元库。为了公平地比较候选算法，我们选择500MHz的参考操作频率。我们的研究结果表明，我们的面积和功率数与现有技术相当，尽管在我们的实验中以更高的操作频率和更高的安全级别为目标。本文对基于格的NIST PQC算法进行了全面的研究，可用于指导ASIC设计人员在选择合适的算法时，同时尊重需求和设计约束。

英文摘要：

Security of currently deployed public key cryptography algorithms is foreseen to be vulnerable against quantum computer attacks. Hence, a community effort exists to develop post-quantum cryptography (PQC) algorithms, i.e., algorithms that are resistant to quantum attacks. In this work, we have investigated how lattice-based candidate algorithms from the NIST PQC standardization competition fare when conceived as hardware accelerators. To achieve this, we have assessed the reference implementations of selected algorithms with the goal of identifying what are their basic building blocks. We assume the hardware accelerators will be implemented in application specific integrated circuit (ASIC) and the targeted technology in our experiments is a commercial 65nm node. In order to estimate the characteristics of each algorithm, we have assessed their memory requirements, use of multipliers, and how each algorithm employs hashing functions. Furthermore, for these building blocks, we have collected area and power figures for 12 candidate algorithms. For memories, we make use of a commercial memory compiler. For logic, we make use of a standard cell library. In order to compare the candidate algorithms fairly, we select a reference frequency of operation of 500MHz. Our results reveal that our area and power numbers are comparable to the state of the art, despite targeting a higher frequency of operation and a higher security level in our experiments. The comprehensive investigation of lattice-based NIST PQC algorithms performed in this paper can be used for guiding ASIC designers when selecting an appropriate algorithm while respecting requirements and design constraints.

机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。

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