硅基III-V激光器中热膨胀诱导位错的缺陷滤波
Defect filtering for thermal expansion induced dislocations in III-V lasers on silicon
摘要：
用于硅光子学的外延集成III-V族半导体激光器具有显著改变信息网络的潜力，但目前，位错限制了性能和可靠性，即使在基于缺陷容限InAs量子点（QD）的激光器中也是如此。尽管低于临界厚度，但这些器件中的QD层包含先前无法解释的失配位错，这有助于非辐射复合。我们在这里证明，这些失配位错形成在生长后冷却期间，由于（1）III-V层和硅之间的热膨胀失配和（2）在有源区中的沉淀和合金硬化的综合影响。通过结合一个额外的亚临界厚度，铟合金失配位错捕获层，我们利用这些机械硬化效应，我们的优势，成功地取代95%的失配位错从模型结构中的QD层。与传统的位错缓解策略不同，捕获层既不减少穿透位错的数量，也不减少失配位错的数量。它只是将失配位错的位置从QD层移开，减少了缺陷对发光的影响。在全激光器中，在QD有源区的上方和下方添加失配位错捕获层可以置换失配位错并大幅提高性能：我们测量到激光阈值电流降低了两倍，输出功率增加了三倍以上。我们的研究结果表明，采用传统的穿线位错减少技术和优化的失配位错捕获层的设备可能最终导致完全集成，商业上可行的硅基光子集成电路。
英文摘要：
Epitaxially integrated III-V semiconductor lasers for silicon photonics have the potential to dramatically transform information networks, but currently, dislocations limit performance and reliability even in defect tolerant InAs quantum dot (QD) based lasers. Despite being below critical thickness, QD layers in these devices contain previously unexplained misfit dislocations, which facilitate non-radiative recombination. We demonstrate here that these misfit dislocations form during post-growth cooldown due to the combined effects of (1) thermal-expansion mismatch between the III-V layers and silicon and (2) precipitate and alloy hardening in the active region. By incorporating an additional sub-critical thickness, indium-alloyed misfit dislocation trapping layer, we leverage these mechanical hardening effects to our advantage, successfully displacing 95% of misfit dislocations from the QD layer in model structures. Unlike conventional dislocation mitigation strategies, the trapping layer reduces neither the number of threading dislocations nor the number of misfit dislocations. It simply shifts the position of misfit dislocations away from the QD layer, reducing the defects' impact on luminescence. In full lasers, adding a misfit dislocation trapping layer both above and below the QD active region displaces misfit dislocations and substantially improves performance: we measure a twofold reduction in lasing threshold currents and a greater than threefold increase in output power. Our results suggest that devices employing both traditional threading dislocation reduction techniques and optimized misfit dislocation trapping layers may finally lead to fully integrated, commercially viable silicon-based photonic integrated circuits.
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