用于CNN推理的ReRAM内存中处理体系结构中延迟减少的SMART路径
SMART Paths for Latency Reduction in ReRAM Processing-In-Memory Architecture for CNN Inference
摘要:
本文提出了一种基于ReRAM的PIM(processing-in-memory)结构,用于快速高效的CNN(卷积神经网络)推理。对于整体架构,我们使用基本的硬件层次结构,如节点,瓦片,核心和子阵列。最重要的是,我们设计了层内流水线,层间流水线,和批流水线,以利用并行的架构,并增加整体吞吐量的输入图像流的推理。我们还优化了片上网络(network-on-chip)路由器的性能,减少跳数使用SMART(单周期多跳异步重复遍历)流量控制。最后,我们针对大规模数据集ImageNet在VGG(A-E)中对不同CNN层进行了权重复制实验。在我们的模拟中,我们实现了40.4027 TOPS(每秒兆操作)的最佳情况下的性能,这相当于超过1029 FPS(每秒帧)。我们还实现了3.5914 TOPS/W(每秒每瓦兆操作数)的最佳情况下的能源效率。此外,与具有基本流水线的基线架构相比,具有积极流水线和权重复制的架构可以实现14倍的加速比,并且与基线相比,SMART流控制在该架构中实现了1.08倍的加速比。最后,我们还评估了智能流量控制的性能,使用合成流量。
英文摘要:
This research work proposes a design of an analog ReRAM-based PIM (processing-in-memory) architecture for fast and efficient CNN (convolutional neural network) inference. For the overall architecture, we use the basic hardware hierarchy such as node, tile, core, and subarray. On the top of that, we design intra-layer pipelining, inter-layer pipelining, and batch pipelining to exploit parallelism in the architecture and increase overall throughput for the inference of an input image stream. We also optimize the performance of the NoC (network-on-chip) routers by decreasing hop counts using SMART (single-cycle multi-hop asynchronous repeated traversal) flow control. Finally, we experiment with weight replications for different CNN layers in VGG (A-E) for large-scale data set ImageNet. In our simulation, we achieve 40.4027 TOPS (tera-operations per second) for the best-case performance, which corresponds to over 1029 FPS (frames per second). We also achieve 3.5914 TOPS/W (tera-operaions per second per watt) for the best-case energy efficiency. In addition, the architecture with aggressive pipelining and weight replications can achieve 14X speedup compared to the baseline architecture with basic pipelining, and SMART flow control achieves 1.08X speedup in this architecture compared to the baseline. Last but not least, we also evaluate the performance of SMART flow control using synthetic traffic.
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