FSNIC：一种用于FPGA智能网卡的低延迟基于流的入侵检测架构
FSNIC: A Low-Latency Flow-Based Intrusion Detection Architecture for FPGA SmartNICs
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中文总结 AI 辅助
针对传统IDS无法线速处理高速流量的问题，提出基于FPGA智能网卡的流级入侵检测架构FSNIC，结合P4解析与LogicNets模型，在UNSW-NB15上准确率从86.92%提升至97.68%，延迟仅6纳秒且资源开销极小。
中文摘要 AI 辅助
现代数据中心需要高性能网络以及有效的实时安全。传统的入侵检测系统（IDS）通常依赖通用处理器，往往难以在不引入延迟或性能瓶颈的情况下以线速检查高速流量。智能网卡（NICs）通过在网络数据平面内直接进行计算提供了一种替代方案。本工作提出了一种在基于FPGA的智能网卡流水线中实现的基于机器学习的IDS。该系统将基于P4的数据包解析与以RTL实现的LogicNets IDS模型相结合，实现了确定性、低延迟的推理。与传统的无状态数据包级分类器相比，所提出的有状态基于流的IDS通过跨数据包聚合特征引入最小的状态，捕获了在数据包级别无法观察到的行为模式。在UNSW-NB15数据集上的实验结果表明，与无状态数据包级分类相比，基于流的IDS将检测准确率从86.92%提高到97.68%。我们还在CICIDS2017上评估了所提出的IDS，并将其实时硬件性能与先前基于FPGA的IDS设计进行了比较。通过硬件-软件协同设计，所提出的IDS实现了6纳秒的推理延迟，仅使用846个LUT，且不使用BRAM或DSP，展示了低延迟和资源高效的实现。
英文摘要
Modern data centres require high-performance networking alongside effective real-time security. Traditional Intrusion Detection Systems (IDS) commonly rely on general-purpose processors and often struggle to inspect high-speed traffic at line rate without introducing latency or performance bottlenecks. Smart Network Interface Cards (NICs) provide an alternative by enabling computation directly within the network data plane. This work presents a machine learning-based IDS implemented within an FPGA-based SmartNIC pipeline. The system integrates P4-based packet parsing with a LogicNets IDS model implemented in RTL, enabling deterministic, low-latency inference. Compared with traditional stateless packet-level classifiers, the proposed stateful flow-based IDS introduces minimal state by aggregating features across packets, capturing behavioural patterns not observable at the packet level. Experimental results on the UNSW-NB15 dataset show that the flow-based IDS improves detection accuracy from 86.92\% to 97.68\% compared with stateless packet-level classification. We also evaluate the proposed IDS on CICIDS2017 and compare its real-time hardware performance with prior FPGA-based IDS designs. Through hardware-software co-design, the proposed IDS achieves 6~ns inference latency using only 846 LUTs, with no BRAM or DSP usage, demonstrating a low latency and resource efficient implementation.
发表机构
- Reconfigurable Computing Systems Lab, Electronic & Electrical Engineering（可重构计算系统实验室，电子与电气工程系）
- Trinity College Dublin（都柏林三一学院）
机构由 AI 辅助整理，请以论文原文为准。
