SLAP：一种分离延迟自适应VLIW流水线架构，其实现动态可变SIMD向量长度
SLAP: A Split Latency Adaptive VLIW pipeline architecture which enables on-the-fly variable SIMD vector-length
摘要：
在过去的十年中，多核访问共享存储器的相对延迟增加，因为线电阻主导延迟，低线密度布局将多端口存储器推到离它们的端口更远的地方。各种技术被部署来改善平均存储器访问延迟，诸如推测性预取和分支预测，这些技术通常导致执行时间的高变化，这在实时的系统中是不可接受的。智能DMA可用于直接将数据复制到第1层SRAM中，但会产生开销。VLIW体系结构，事实上的信号处理引擎，遭受严重的故障锁步执行标量和向量指令。我们描述了分割延迟自适应流水线（SSENT）VLIW架构，高速缓存性能的改善技术，需要零更改的目标代码，同时消除智能DMA和它们的开销。Scrum建立在解耦访问和执行概念的基础上，通过1）打破功能单元的锁步执行，2）为可变数据级并行启用可变向量长度，以及3）添加新的三角加载机制。我们讨论了Sunday架构，并展示了从无线基带系统（即使是最计算密集型的功能遭受的Amdahls定律的限制，由于标量和矢量处理的混合）的真实轨迹的性能优势。
英文摘要：
Over the last decade the relative latency of access to shared memory by multicore increased as wire resistance dominated latency and low wire density layout pushed multiport memories farther away from their ports. Various techniques were deployed to improve average memory access latencies, such as speculative pre-fetching and branch-prediction, often leading to high variance in execution time which is unacceptable in real time systems. Smart DMAs can be used to directly copy data into a layer1 SRAM, but with overhead. The VLIW architecture, the de facto signal processing engine, suffers badly from a breakdown in lockstep execution of scalar and vector instructions. We describe the Split Latency Adaptive Pipeline (SLAP) VLIW architecture, a cache performance improvement technology that requires zero change to object code, while removing smart DMAs and their overhead. SLAP builds on the Decoupled Access and Execute concept by 1) breaking lockstep execution of functional units, 2) enabling variable vector length for variable data level parallelism, and 3) adding a novel triangular load mechanism. We discuss the SLAP architecture and demonstrate the performance benefits on real traces from a wireless baseband system (where even the most compute intensive functions suffer from an Amdahls law limitation due to a mixture of scalar and vector processing).
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
