自适应延迟DRAM：通过利用定时裕量来减少DRAM延迟
Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins
摘要：
本文总结了HPCA 2015上发表的自适应延迟DRAM（AL-DRAM）的想法，并探讨了这项工作的意义和未来潜力。AL-DRAM是一种基于DRAM模块和操作温度，通过利用内置于DRAM时序参数中的额外裕度来优化DRAM延迟的机制。DRAM制造商为时序参数提供了较大的裕度，作为对两种最坏情况的准备。首先，由于工艺差异，一些异常的DRAM芯片比其他芯片慢得多。其次，芯片在较高温度下变得较慢。定时参数裕度确保了慢异常值芯片在最坏情况温度下可靠地操作，并且因此导致高访问延迟。使用基于FPGA的DRAM测试平台，我们的工作首先表征了来自三个主要制造商的115个DRAM模块的额外裕度。实验结果表明，它是可能的，以最小/最大的17.3%/54.8%，在55 ℃，同时保持可靠的操作，减少四个最关键的定时参数。AL-DRAM使用这些观察来基于模块的当前操作条件自适应地为每个DRAM模块选择可靠的DRAM定时参数。AL-DRAM不需要对DRAM芯片或其接口进行任何更改;它只需要内存控制器指定和支持多个不同的时序参数。我们的真实系统评估表明，AL-DRAM将内存密集型工作负载的性能平均提高了14%，而不会引入任何错误。我们的表征和提出的技术启发了其他几个工作分析和/或利用DRAM芯片内的延迟和性能变化的不同来源。
英文摘要：
This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was published in HPCA 2015, and examines the work's significance and future potential. AL-DRAM is a mechanism that optimizes DRAM latency based on the DRAM module and the operating temperature, by exploiting the extra margin that is built into the DRAM timing parameters. DRAM manufacturers provide a large margin for the timing parameters as a provision against two worst-case scenarios. First, due to process variation, some outlier DRAM chips are much slower than others. Second, chips become slower at higher temperatures. The timing parameter margin ensures that the slow outlier chips operate reliably at the worst-case temperature, and hence leads to a high access latency. Using an FPGA-based DRAM testing platform, our work first characterizes the extra margin for 115 DRAM modules from three major manufacturers. The experimental results demonstrate that it is possible to reduce four of the most critical timing parameters by a minimum/maximum of 17.3%/54.8% at 55C while maintaining reliable operation. AL-DRAM uses these observations to adaptively select reliable DRAM timing parameters for each DRAM module based on the module's current operating conditions. AL-DRAM does not require any changes to the DRAM chip or its interface; it only requires multiple different timing parameters to be specified and supported by the memory controller. Our real system evaluations show that AL-DRAM improves the performance of memory-intensive workloads by an average of 14% without introducing any errors. Our characterization and proposed techniques have inspired several other works on analyzing and/or exploiting different sources of latency and performance variation within DRAM chips.
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