高速DDR5和LPDDR5/6内存控制器自动化预硅验证：UVM中的闭环时序、模式寄存器与PHY同步
Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
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中文总结 AI 辅助
本文提出一种自动化预硅验证框架，通过解析JEDEC参数、MR-RAL跟踪和动态PHY初始化，实现DDR5/LPDDR5/6内存控制器的闭环配置与随机化测试，消除设置开销并防止协议违规。
中文摘要 AI 辅助
外部存储器接口（如LPDDR5/4和DDR5）是现代移动、云和企业计算系统的重要组成部分。虽然存储器制造商专注于物理DRAM芯片的开发，但绝大多数半导体公司设计定制应用ASIC，需要专用的内存控制器（Memory Controller）来与这些标准化的外部存储器进行接口。因此，内存控制器RTL（作为被测设备DUT，与第三方DRAM验证IP（VIP）进行交互）的预硅设计验证是全球半导体行业中普遍存在且至关重要的挑战。本文提出了一种用于内存控制器验证的自动化预硅配置和闭环初始化框架。所提出的解决方案直接从DRAM VIP的数据库文件（如Denali SOMA文件）中解析JEDEC时序和配置参数，以配置内存控制器DUT的寄存器，同时自定义的模式寄存器寄存器抽象层（MR-RAL）实时跟踪易失性DRAM VIP状态。此外，一种动态的、无需重新编译的PHY初始化流程直接在测试平台中随机化接口参数，通过系统调用执行即时配置生成，并在运行时解析生成的寄存器写入序列。通过将这些自动化方法集成到预硅验证流程中，工程师可以消除设置开销，防止错误的协议违规，并实现对复杂PHY和内存控制器配置的全面随机化测试。
英文摘要
External memory interfaces (such as LPDDR5/4 and DDR5) are essential components of modern mobile, cloud, and enterprise computing systems. While memory manufacturers focus on physical DRAM die development, the vast majority of semiconductor firms design custom application ASICs that require a dedicated Memory Controller to interface with these standardized external memories. Consequently, pre-silicon design verification of the Memory Controller RTL -- acting as the Device Under Test (DUT) against a third-party DRAM Verification IP (VIP) -- is a ubiquitous and critical challenge across the global semiconductor industry. This article presents an automated, pre-silicon configuration and closed-loop initialization framework for Memory Controller verification. The proposed solution parses JEDEC timing and configuration parameters directly from the DRAM VIP's database files (such as Denali SOMA files) to configure the Memory Controller DUT's registers, while a custom Mode Register Register Abstraction Layer (MR-RAL) tracks volatile DRAM VIP states in real-time. Furthermore, a dynamic, re-compilation-free PHY initialization flow randomizes interface parameters directly in the testbench, executes on-the-fly configuration generation via system calls, and parses the resulting register write sequences at runtime. By integrating these automated methodologies into pre-silicon verification flows, engineers can eliminate setup overhead, prevent false protocol violations, and enable comprehensive randomized testing of complex PHY and Memory Controller configurations.
发表机构
- Google LLC（谷歌有限责任公司）
- Google IT Services India Pvt. Ltd.（谷歌印度信息技术服务私人有限公司）
机构由 AI 辅助整理，请以论文原文为准。
