具有延迟抽象接口的参数化硬件设计
Parameterized Hardware Design with Latency-Abstract Interfaces
AI总结：
本文提出延迟抽象接口，通过参数化HDL实现时间适应性，确保设计在接口变化时仍具高效性能。
摘要：
硬件设计在输入依赖于时间时必须使用延迟不敏感（LI）接口。当时间与输入无关时，设计应使用延迟敏感（LS）接口以获得最大性能。然而，设计通常使用LI接口与外部生成的LS模块集成——例如IP生成器、高级综合或领域特定语言。在每个完全集成的设计中，此类LI接口的使用都代表纯粹的开销。挑战在于生成器可以大幅改变模块的时间接口以满足性能目标，而LI接口则作为有用的 设计抽象，使时间适应成为可能。我们定义了延迟抽象（LA）接口，这是一种新的设计抽象，它在设计时提供LI接口的时间适应性，并在设计时提供LS接口的高效集成。LA接口使用输出参数，一种新的编译时机制，使子模块能够将值返回给父模块，以抽象和封装设计时的时间行为。在设计展开过程中，LA接口根据参数值被编译成高效的LS接口。虽然这是一个有吸引力的选择，但LA接口继承了参数化硬件设计的复杂性：用户必须思考参数如何影响模块的时间行为，并确保设计适应接口变化。为了解决这一挑战并证明LA接口的实用性，我们设计了Lilac，一种参数化HDL，它使用类型系统跟踪参数对时间行为的影响，并正式保证每个LA设计的参数化都会产生一个没有结构危险的电路。
英文摘要：
Hardware designs must use latency-insensitive (LI) interfaces when timing is input-dependent. When timing is input-independent, designs should use latency-sensitive (LS) interfaces for maximum performance. However, designs commonly use LI interfaces to integrate with externally generated LS modules--from, e.g., IP generators, high-level synthesis, or domain specific languages. In every fully integrated design, such uses of LI represent pure overhead. The challenge is that generators can dramatically change timing interfaces of the modules to meet performance objectives, and LI interfaces act as a useful design abstraction and enable timing adaptation. We define latency-abstract (LA) interfaces, a new design abstraction, which provide the timing adaptability of LI interfaces at design-time and the efficient integration of LS interfaces. LA interfaces use output parameters, a novel compile-time mechanism for child modules to return values parent modules, to abstract and encapsulate timing behaviors at design time. During design elaboration, LA interfaces are compiled into efficient LS interfaces based on parameter values. While an attractive option, LA interfaces inherit the complexities of parameterized hardware design: the user must reason how parameters influence timing behaviors of modules and ensure that designs adapt to interface changes. To address this challenge and demonstrate the utility of LA interfaces, we design Lilac, a parameterized HDL that uses a type system track the influence of parameters on timing behaviors and formally guarantee that every parameterization of an LA design results in a circuit without structural hazards.
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