OpenRISC片上系统设计仿真
OpenRISC System-on-Chip Design Emulation
摘要：
近年来，硬件仿真技术已成为加速硬件验证/调试过程的一种很有前途的方法。为了充分评估仿真方法的强大功能并展示其潜在影响，我们建议使用Mentor Graphics Veloce仿真平台来仿真片上系统（SoC）设计。本文介绍了我们的项目设置和我们取得的成果。结果令人鼓舞。使用Veloce的ORPSoC仿真比硬件仿真快十倍以上。我们的实验结果表明，Mentor Graphics Veloce在仿真，验证和调试复杂的实际硬件设计方面具有重大优势，特别是在SoC复杂性的背景下。通过我们的三个主要任务，我们将证明（1）Veloce可以成功地仿真大规模SoC设计;（2）与最先进的仿真工具相比，它具有更好的性能;（3）它可以显着加快硬件验证和调试的过程，同时保持完整的信号可见性。
英文摘要：
Recently the hardware emulation technique has emerged as a promising approach to accelerating hardware verification/debugging process. To fully evaluate the powerfulness of the emulation approach and demonstrate its potential impact, we propose to emulate a system-on-chip (SoC) design using Mentor Graphics Veloce emulation platform. This article presents our project setup and the results we have achieved. The results are encouraging. ORPSoC emulation with Veloce has more than ten times faster than hardware simulation. Our experimental results demonstrate that Mentor Graphics Veloce has major advantages in emulation, verification, and debugging of complicated real hardware designs, especially in the context of SoC complexity. Through our three major tasks, we will demonstrate that (1) Veloce can successfully emulate large-scale SoC designs; (2) it has much better performance comparing to the state-of-the-art simulation tools; (3) it can significantly accelerate the process of hardware verification and debugging while maintaining full signal visibility.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
