针对多处理器和动力系统控制系统SoCs的支持、校准和仿真
Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs
摘要：
具有多个处理器内核的复杂SoC的引入带来了新的开发挑战，因此开发支持现在是选择片上系统（SoC）的决定性因素。所提出的发展支助战略利用架构和技术方法应对挑战。多核中断支持（MCDS）架构使用交叉触发器和多核中断和挂起开关提供灵活的触发。通过片上时间戳，保证时间跟踪顺序下降到周期级别。封装尺寸ICE（PSI）方法是一种在不改变器件行为的情况下包括跟踪缓冲器、覆盖存储器、处理资源和通信接口的新颖方法。PSI不需要外部仿真盒，因为调试主机使用标准接口直接与SoC连接。
英文摘要：
The introduction of complex SoCs with multiple processor cores presents new development challenges, such that development support is now a decisive factor when choosing a System-on-Chip (SoC). The presented developments support strategy addresses the challenges using both architecture and technology approaches. The Multi-Core Debug Support (MCDS) architecture provides flexible triggering using cross triggers and a multiple core break and suspend switch. Temporal trace ordering is guaranteed down to cycle level by on-chip time stamping. The Package Sized-ICE (PSI) approach is a novel method of including trace buffers, overlay memories, processing resources and communication interfaces without changing device behavior. PSI requires no external emulation box, as the debug host interfaces directly with the SoC using a standard interface.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
