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arXiv 1502.05748cs.LO
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硬件电路设计与验证的多值逻辑方法

A Multiple-Valued Logic Approach to the Design and Verification of Hardware Circuits

Amnon Rosenmann

摘要:

我们提出了一种新的方法,这是基于多值逻辑(MVL),数字硬件设计的验证和分析,扩展了常见的三进制或四进制模拟方法。在信息量更大的MVL设置中执行的模拟揭示了通过二进制或三进制模拟不可见或难以检测的细节。在等效性验证中,在MVL模拟下检测不同的行为可能会导致发现真正的二元不等效性或两个设计之间的定性差距。模拟中变量的值可能包含有关其真实程度以及“出生地”和“出生日期”的信息。应用包括等价性验证、初始化、断言生成和验证、通过优先级排序和面向块的模拟对数据流进行部分控制。本文的大部分内容都致力于MVL方法背后的理论方面,包括选择特定代数进行计算的原因,以及布尔表达式的验证复杂性的介绍。两个基本算法。

英文摘要:

We present a novel approach, which is based on multiple-valued logic (MVL), to the verification and analysis of digital hardware designs, which extends the common ternary or quaternary approaches for simulations. The simulations which are performed in the more informative MVL setting reveal details which are either invisible or harder to detect through binary or ternary simulations. In equivalence verification, detecting different behavior under MVL simulations may lead to the discovery of a genuine binary nonequivalence or to a qualitative gap between two designs. The value of a variable in a simulation may hold information about its degree of truth and its "place of birth" and "date of birth." Applications include equivalence verification, initialization, assertions generation and verification, partial control on the flow of data by prioritizing and block-oriented simulations. Much of the paper is devoted to theoretical aspects behind the MVL approach, including the reason for choosing a specific algebra for computations, and the introduction of the verification complexity of a Boolean expression. Two basic algorithms are presented.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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