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arXiv 1403.7380cs.AR
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生成和评估特定于应用的硬件扩展

Generating and evaluating application-specific hardware extensions

Nikolaos Kavvadias

摘要:

现代基于平台的设计涉及嵌入式处理器的特定应用扩展,以满足客户需求。为了完成这一任务,最近的定制/可扩展处理器提供的可能性,调整其指令集和微体系结构的应用感兴趣的,必须加以利用。通常决定此过程成功的一个重要因素是应用程序分析和自定义指令生成中可用的自动化。在本文中,我们提出了YARDstick,一个设计自动化工具的定制处理器开发流程,重点是生成和评估特定于应用程序的硬件扩展。YARDstick是ASIP开发的构建块,它集成了应用程序分析、自定义指令生成和选择以及用户定义的编译器中间表示。在一个YARDstick启用的环境中,在传统的ASIP设计的实际问题面临有效的,探索基础设施从编译器和模拟器的特质解放出来,因为ASIP设计师被赋予了自由指定的目标体系结构的选择和添加新的实现的分析和自定义指令生成/选择方法。为了说明YARDstick方法的能力,我们提出了有趣的探索方案:量化机器相关的编译器优化和目标体系结构的选择方面的操作集和内存模型的自定义指令生成/选择不同的输入/输出约束下的效果。

英文摘要:

Modern platform-based design involves the application-specific extension of embedded processors to fit customer requirements. To accomplish this task, the possibilities offered by recent custom/extensible processors for tuning their instruction set and microarchitecture to the applications of interest have to be exploited. A significant factor often determining the success of this process is the utomation available in application analysis and custom instruction generation. In this paper we present YARDstick, a design automation tool for custom processor development flows that focuses on generating and evaluating application-specific hardware extensions. YARDstick is a building block for ASIP development, integrating application analysis, custom instruction generation and selection with user-defined compiler intermediate representations. In a YARDstick-enabled environment, practical issues in traditional ASIP design are confronted efficiently; the exploration infrastructure is liberated from compiler and simulator idiosyncrasies, since the ASIP designer is empowered with the freedom of specifying the target architectures of choice and adding new implementations of analyses and custom instruction generation/selection methods. To illustrate the capabilities of the YARDstick approach, we present interesting exploration scenarios: quantifying the effect of machine-dependent compiler optimizations and the selection of the target architecture in terms of operation set and memory model on custom instruction generation/selection under different input/output constraints.

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