评估微架构硬件故障检测对特定应用需求的有效性
Evaluating the Effectiveness of Microarchitectural Hardware Fault Detection for Application-Specific Requirements
AI总结：
本文系统评估了DMR、R-SMT和ParDet三种硬件故障检测方法在面积、功耗、性能和检测延迟等方面的表现，揭示微架构级方法虽具可比鲁棒性，但在特定实际应用中仍存在不利权衡。
摘要：
可靠性在涵盖众多领域的安全关键应用中必不可少。传统的基于硬件的容错技术（例如组件冗余）能够确保可靠性，但通常以显著增加的功耗以及几乎翻倍（或更多）的硬件面积为代价。为了降低这些成本，微架构容错方法试图通过利用微架构层面的洞察来减少开销，但先前的研究主要只关注应用性能。由于不同的安全关键应用在可靠性之外还优先考虑不同的需求，仅评估有限的指标无法保证微架构方法对所有不同应用场景都切实可行且可用。为此，在本工作中，我们广泛地刻画并比较了三种故障检测方法，每种方法代表一个不同的主要故障检测类别，同时考虑来自多样化应用场景的真实需求，并采用设计面积、功耗、性能开销和检测延迟等多种重要指标。通过这一分析，我们提供了重要的见解，可以指导设计人员针对特定需求应用最有效的容错方法，从而推进对鲁棒计算系统的整体理解和发展。为此，我们研究了处理器内部硬件错误检测的三种方法，即：（i）双模块冗余（DMR）作为一种传统方法，以及（ii）冗余多线程（R-SMT）和（iii）并行错误检测（ParDet）作为微架构级方法。我们证明，微架构容错方法（即 R-SMT 和 ParDet）与传统方法（DMR）相比具有相当的鲁棒性，但对于特定的实际使用场景仍表现出不具吸引力的权衡，从而阻碍了它们在某些应用场景中的使用。
英文摘要：
Reliability is necessary in safety-critical applications spanning numerous domains. Conventional hardware-based fault tolerance techniques, such as component redundancy, ensure reliability, typically at the expense of significantly increased power consumption, and almost double (or more) hardware area. To mitigate these costs, microarchitectural fault tolerance methods try to lower overheads by leveraging microarchitectural insights, but prior evaluations focus primarily on only application performance. As different safety-critical applications prioritize different requirements beyond reliability, evaluating only limited metrics cannot guarantee that microarchitectural methods are practical and usable for all different application scenarios. To this end, in this work, we extensively characterize and compare three fault detection methods, each representing a different major fault detection category, considering real requirements from diverse application settings and employing various important metrics such as design area, power, performance overheads and latency in detection. Through this analysis, we provide important insights which may guide designers in applying the most effective fault tolerance method tailored to specific needs, advancing the overall understanding and development of robust computing systems. For this, we study three methods for hardware error detection within a processor, i.e., (i) Dual Modular Redundancy (DMR) as a conventional method, and (ii) Redundant Multithreading (R-SMT) and (iii) Parallel Error Detection (ParDet) as microarchitecture-level methods. We demonstrate that microarchitectural fault tolerance, i.e., R-SMT and ParDet, is comparably robust compared to conventional approaches (DMR), however, still exhibits unappealing trade-offs for specific real-world use cases, thus precluding their usage in certain application scenarios.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
