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arXiv 1105.0682quant-ph
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电子学约束对固态量子纠错和量子线路失效概率的影响

Implications of Electronics Constraints for Solid-State Quantum Error Correction and Quantum Circuit Failure Probability

James E. Levy, Malcolm S. Carroll, Anand Ganti, Cynthia A. Phillips, Andrew J. Landahl, Thomas M. Gurrieri, Robert D. Carr, Harold L. Stalford, Erik Nielsen

摘要:

在本文中,我们介绍了经典电子学约束对固态量子点逻辑量子比特架构的影响。由于路由密度、带宽分配、信号定时和经典支持电子器件的热感知放置的约束显著影响量子纠错电路的错误率。我们分析一个级别的量子纠错电路使用九个数据量子比特的培根肖尔码配置为量子存储器。一个假想的硅双量子点量子位(qubit)被用作基本元素。一个悲观估计的错误概率的量子线路计算使用门的总数和空闲时间,使用可证明的最佳时间表的电路操作与整数规划方法。微架构分析提供了关于电子器件影响电路性能的不同方式的见解(例如,时间表中的额外空闲时间),这会显著限制任何量子线路的最终性能,因此是任何未来更大规模架构分析的关键基础。

英文摘要:

In this paper we present the impact of classical electronics constraints on a solid-state quantum dot logical qubit architecture. Constraints due to routing density, bandwidth allocation, signal timing, and thermally aware placement of classical supporting electronics significantly affect the quantum error correction circuit's error rate. We analyze one level of a quantum error correction circuit using nine data qubits in a Bacon-Shor code configured as a quantum memory. A hypothetical silicon double quantum dot quantum bit (qubit) is used as the fundamental element. A pessimistic estimate of the error probability of the quantum circuit is calculated using the total number of gates and idle time using a provably optimal schedule for the circuit operations obtained with an integer program methodology. The micro-architecture analysis provides insight about the different ways the electronics impact the circuit performance (e.g., extra idle time in the schedule), which can significantly limit the ultimate performance of any quantum circuit and therefore is a critical foundation for any future larger scale architecture analysis.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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