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arXiv 2604.03396cs.CR
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通用电路的安全性分析:作为硬件混淆机制的机制

Security Analysis of Universal Circuits as a Mechanism for Hardware Obfuscation

University of Idaho(爱达荷大学);Carnegie Mellon University(卡内基梅隆大学)

Zain Ul Abideen, Deepali Garg, Lawrence Pileggi, Samuel Pagliarini

AI总结:

研究通用电路在硬件知识产权保护中的安全性,评估了状态最新oracle引导和无oracle攻击下的表现,证明其在保护IP方面的可行性。

摘要:

通用电路(UCs)提供了一种有前途的方法来对硬件知识产权(IP)进行混淆,利用密码学原理来隐藏可编程逻辑织物中的结构和功能。它们的适应性使其特别适合全球化的集成电路(IC)供应链,其中对反向工程等威胁的安全性至关重要。尽管有潜力,UC的安全性仍大多未被探索。本文评估了UC对最新oracle引导(OG)和无oracle(OL)攻击的安全性。结果表明,OG攻击的成功率接近随机(约50%),而OL攻击显示了最小的结构泄露。总体而言,这些发现证实了UCs在IP保护方面的可行性。

英文摘要:

Universal Circuits (UCs) offer a promising approach to hardware Intellectual Property (IP) obfuscation, leveraging cryptographic principles to hide both structure and function in a programmable logic fabric. Their adaptability makes them especially suitable for the globalized Integrated Circuit (IC) supply chain, where security against threats like reverse engineering is crucial. Despite the potential, UC security remains largely unexplored. This work evaluates UC security against state-of-the-art oracle-guided (OG) and oracle-less (OL) attacks. Results show near-random success rates (approx 50%) for OG attacks whereas OL attacks display minimal structural leakage. Collectively, these findings confirm the feasibility of UCs for IP protection.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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