On-device tuning of deep neural networks enables long-term adaptation at the edge while preserving data privacy. However, the high computational and memory demands of backpropagation pose significant challenges for ultra-low-power, memory-constrained extreme-edge devices. These challenges are further amplified for attention-based models due to their architectural complexity and computational scale. We present TrainDeeploy, a framework that unifies efficient inference and on-device training on heterogeneous ultra-low-power System-on-Chips (SoCs). TrainDeeploy provides the first complete on-device training pipeline for extreme-edge SoCs supporting both Convolutional Neural Networks (CNNs) and Transformer models, together with multiple training strategies such as selective layer-wise fine-tuning and Low-Rank Adaptation (LoRA). On a RISC-V-based heterogeneous SoC, we demonstrate the first end-to-end on-device fine-tuning of a Compact Convolutional Transformer (CCT), achieving up to 11 trained images per second. We show that LoRA reduces dynamic memory usage by 23%, decreases the number of trainable parameters and gradients by 15x, and reduces memory transfer volume by 1.6x compared to full backpropagation. TrainDeeploy achieves up to 4.6 FLOP/cycle on CCT (0.28M parameters, 71-126M FLOPs) and up to 13.4 FLOP/cycle on Deep-AE (0.27M parameters, 0.8M FLOPs), while expanding the scope of prior frameworks to support both CNN and Transformer models with parameter-efficient tuning on extreme-edge platforms.
Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
SKLP, Institute of Computing Technology, Chinese Academy of Sciences（中国科学院计算技术研究所）；University of Chinese Academy of Sciences（中国科学院大学）；Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences（中国科学院深圳先进技术研究院）；Southern University of Science and Technology（南方科技大学）；Shenzhen University of Advanced Technology（深圳先进技术研究院）
TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences（处理器国家重点实验室，中国科学院计算技术研究所）；University of Chinese Academy of Sciences（中国科学院大学）；University of Cambridge（剑桥大学）；The University of Sydney（悉尼大学）
Enabling Physical AI at the Edge: Hardware-Accelerated Recovery of System Dynamics
School of Electrical Engineering Arizona State University Tempe, USA（电气工程学院亚利桑那州立大学Tempe分校）；School of Computing Science Arizona State University Tempe, USA（计算科学学院亚利桑那州立大学Tempe分校）
Cloud to Edge: Benchmarking LLM Inference On Hardware-Accelerated Single-Board Computers
Kaze Technologies（凯兹技术）；Kaze Consulting（凯兹咨询）；Electrical and Computer Engineering（电气与计算机工程）；Lebanese American University（黎巴嫩美国大学）；Carnegie Mellon University（卡内基梅隆大学）；University of Exeter（埃克塞特大学）
FireFly-P: FPGA-Accelerated Spiking Neural Network Plasticity for Robust Adaptive Control
Center for Long-term Artificial Intelligence（长期人工智能中心）；Beijing Institute of AI Safety and Governance（北京人工智能安全与治理研究院）；School of Future Technology（未来技术学院）；School of Artificial Intelligence, University of Chinese Academy of Sciences（中国科学院大学人工智能学院）；Key Laboratory of Brain Cognition and Brain-inspired Intelligence Technology, Chinese Academy of Sciences（中国科学院脑认知与脑启智技术重点实验室）；Brain-inspired Cognitive Intelligence Lab, Institute of Automation, Chinese Academy of Sciences（中国科学院自动化研究所脑启智认知智能实验室）
ESL-former: Event Sparse Linear Transformer for FPGA-Accelerated Malware Detection
School of Computer Science and Engineering, Changsha University（长沙大学计算机科学与工程学院）；Electronics and Electrical Engineering, Trinity College Dublin（都柏林三一学院电子与电气工程系）
