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arXiv 2512.06643cs.LO
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功能简化以加快边界模型检查

Functional Reduction to Speed Up Bounded Model Checking

Hong Kong University of Science and Technology (Guangzhou)(香港科技大学(广州))

Changyuan Yu, Wenbin Che, Hongce Zhang

AI总结:

FRAIG-BMC通过功能简化减少冗余,提升边界模型检查的效率和性能。

摘要:

边界模型检查(BMC)是一种广泛用于形式化属性验证(FPV)的技术,其中转移关系被反复展开到越来越深的深度,并编码成布尔可满足性(SAT)查询。随着界限的增长,这些SAT查询通常变得越来越难解决,带来了可扩展性挑战。然而,许多FPV问题涉及多个相关电路的副本,这创造了简化展开的转移关系的机会。受功能简化和-反演图(FRAIG)技术的启发,我们提出了FRAIG-BMC,该技术在展开过程中逐步识别并合并功能等价的节点。通过减少冗余,FRAIG-BMC提高了SAT求解的效率并加速了属性检查。实验表明,FRAIG-BMC在各种应用中显著加快了BMC的速度,包括顺序等价性检查、部分保留寄存器检测和信息流检查。

英文摘要:

Bounded model checking (BMC) is a widely used technique for formal property verification (FPV), where the transition relation is repeatedly unrolled to increasing depths and encoded into Boolean satisfiability (SAT) queries. As the bound grows deeper, these SAT queries typically become more difficult to solve, posing scalability challenges. Howevefor, many FPV problems involve multiple copies of related circuits, creating opportunities to simplify the unrolled transition relation. Motivated by the functionally reduced and-inverter-graph (FRAIG) technique, we propose FRAIG-BMC, which incrementally identifies and merges functionally equivalent nodes during the unrolling process. By reducing redundancy, FRAIG-BMC improves the efficiency of SAT solving and accelerates property checking. Experiments demonstrate that FRAIG-BMC significantly speeds up BMC across a range of applications, including sequential equivalence checking, partial retention register detection, and information flow checking

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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