基于SoCMake的硬件与软件构建流程
Hardware and software build flow with SoCMake
AI总结：
针对现有硬件构建系统对软件编译支持不足的问题，CERN开发了开源构建工具SoCMake，统一支持硬件设计流程与C++/C/汇编交叉编译，用于自动生成容错RISC-V SoC。
摘要：
对电子产品日益增长的需求正在推动专用集成电路（ASIC）开发周期的缩短。为满足这些约束，硬件设计人员强调IP模块的可复用性和模块化，利用集成处理器和通用互连的标准片上系统（SoC）架构。虽然这些架构减少了设计和验证工作量，但它们也引入了复杂性，因为验证必须同时涵盖硬件和软件执行。为增强可复用性，硬件IP模块通常采用更高抽象级别的语言（如Chisel和SystemRDL）进行描述，依靠编译器生成用于RTL仿真和实现的Verilog。在系统层面，SoC建模和验证利用C++和SystemC，凸显了软件编译的必要性。因此，有效的构建系统必须同时支持硬件设计流程和软件编译，包括针对C++、C和汇编的交叉编译。现有的硬件构建系统对软件编译的支持不足，因此需要开发新的解决方案。为此，CERN微电子部门启动了SoCMake项目，最初作为片上系统抗辐射生态系统（SOCRATES）的一部分。SoCMake旨在自动生成适用于高能物理环境的容错RISC-V SoC，此后已发展成为一个通用的开源SoC生成构建工具。
英文摘要：
The increasing demand for electronics is driving shorter development cycles for application-specific integrated circuits (ASICs). To meet these constraints, hardware designers emphasize reusability and modularity of IP blocks, leveraging standard system-on-chip (SoC) architectures with integrated processors and common interconnects. While these architectures reduce design and verification efforts, they also introduce complexity, as verification must encompass both hardware and software execution. To enhance reusability, hardware IP blocks are often described in higher-abstraction-level languages such as Chisel and SystemRDL, relying on compilers to generate Verilog for RTL simulation and implementation. At the system level, SoC modeling and verification leverage C++ and SystemC, underscoring the need for software compilation. Consequently, an effective build system must support both hardware design flows and software compilation, including cross-compilation for C++, C, and assembly. Existing hardware build systems lack sufficient support for software compilation, necessitating the development of a new solution. In response, the Microelectronics section of CERN initiated SoCMake, initially as part of the System-on-Chip Radiation Tolerant Ecosystem (SOCRATES). Designed to automate the generation of fault-tolerant RISC-V SoCs for high-energy physics environments, SoCMake has since evolved into a generic open-source build tool for SoC generation.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
