使用Chisel和Scala进行开源验证
Open-Source Verification with Chisel and Scala
摘要：
通用处理器的性能增长已停止。我们不能再依赖摩尔定律来提高计算性能。实现更高性能或更低能耗的唯一方法是构建特定领域的硬件加速器。为了有效地设计和验证这些特定领域的加速器，我们需要敏捷的硬件开发。提出这种现代方法的主要障碍之一是缺乏现代工具来攻击它。为了能够在这种时间约束的开发方法中验证设计，需要有有效的设计和验证工具。因此，本文提出了ChiselVerify，一个开源工具，用于验证任何硬件描述语言中描述的电路。它建立在Chisel硬件构造语言之上，并使用Scala来驱动验证，使用受通用验证方法（UVM）启发的测试策略，并适用于Chisel中描述的设计。ChiselVerify基于三个关键思想创建。首先，我们的解决方案允许在现代高级编程环境中进行硬件测试，从而大大提高了验证工程师的工作效率。其次，由于Chisel黑盒的灵活性，该框架可以使用任何硬件描述语言。最后，该解决方案很好地集成到现有的Chisel宇宙中，使其成为当前现有测试库的扩展。我们实现ChiselVerify在SystemVerilog中发现的功能的启发方式。这允许在当代高级编程生态系统中的设计验证过程中使用功能覆盖、约束随机验证、总线功能模型、事务级建模等等。
英文摘要：
Performance increase with general-purpose processors has come to a halt. We can no longer depend on Moore's Law to increase computing performance. The only way to achieve higher performance or lower energy consumption is by building domain-specific hardware accelerators. To efficiently design and verify those domain-specific accelerators, we need agile hardware development. One of the main obstacles when proposing such a modern method is the lack of modern tools to attack it. To be able to verify a design in such a time-constrained development method, one needs to have efficient tools both for design and verification. This paper thus proposes ChiselVerify, an open-source tool for verifying circuits described in any Hardware Description Language. It builds on top of the Chisel hardware construction language and uses Scala to drive the verification using a testing strategy inspired by the Universal Verification Methodology (UVM) and adapted for designs described in Chisel. ChiselVerify is created based on three key ideas. First, our solution highly increases the productivity of the verification engineer, by allowing hardware testing to be done in a modern high-level programming environment. Second, the framework functions with any hardware description language thanks to the flexibility of Chisel blackboxes. Finally, the solution is well integrated into the existing Chisel universe, making it an extension of currently existing testing libraries. We implement ChiselVerify in a way inspired by the functionalities found in SystemVerilog. This allows one to use functional coverage, constrained-random verification, bus functional models, transaction-level modeling and much more during the verification process of a design in a contemporary high-level programming ecosystem.
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