Large Language Models (LLMs) have become increasingly popular for generating RTL code. However, producing error-free RTL code in a zero-shot setting remains highly challenging for even state-of-the-art LLMs, often leading to issues that require manual, iterative refinement. This additional debugging process can dramatically increase the verification workload, underscoring the need for robust, automated correction mechanisms to ensure code correctness from the start.
In this work, we introduce AIvril2, a self-verifying, LLM-agnostic agentic framework aimed at enhancing RTL code generation through iterative corrections of both syntax and functional errors. Our approach leverages a collaborative multi-agent system that incorporates feedback from error logs generated by EDA tools to automatically identify and resolve design flaws. Experimental results, conducted on the VerilogEval-Human benchmark suite, demonstrate that our framework significantly improves code quality, achieving nearly a 3.4$\times$ enhancement over prior methods. In the best-case scenario, functional pass rates of 77% for Verilog and 66% for VHDL were obtained, thus substantially improving the reliability of LLM-driven RTL code generation.
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
School of Integrated Circuits, Southeast University（东南大学集成电路学院）；National Center of Technology Innovation for EDA（国家EDA技术创新中心）；College of Economics, Shenzhen University（深圳大学经济学院）；School of Computer Science and Engineering, Sun Yat-sen University（中山大学计算机科学与工程学院）；Department of Computer Science, University of York（约克大学计算机科学系）；Department of Computer Science, City University of Hong Kong（香港城市大学计算机科学系）
ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning
SKLP, Institute of Computing Technology, Chinese Academy of Sciences（中国科学院计算技术研究所智能计算机研究中心）；University of Chinese Academy of Sciences（中国科学院大学）；University of Electronic Science and Technology of China（电子科技大学）；Beijing Institute of Technology（北京理工大学）
Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
Zhejiang University \& Northwestern Polytechnical University China；Northwestern Polytechnical University China；Nantong University China；Zhejiang University China；Monash University Australia；Singapore Management University Singapore；Zhejiang University \& Northwestern Polytechnical University；Northwestern Polytechnical University；Nantong University；Zhejiang University；Monash University；Singapore Management University
RTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning
State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences（中国科学院计算技术研究所处理器国家重点实验室）；University of Chinese Academy of Sciences（中国科学院大学）；Peking University（北京大学）；CASTEST Co., Ltd.（中科芯测科技有限公司）
Veri-Sure: Multi-Agent RTL Code Generation with Temporal Tracing, Slicing and Formal Verification
School of Physics and Astronomy, The University of Edinburgh, Edinburgh, UK（物理与天文学院，爱丁堡大学，爱丁堡，英国）；State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau（模拟与混合信号VLSI国家重点实验室，澳门大学，澳门）；School of Science and Engineering, The Chinese University of Hong Kong, Shenzhen, Shenzhen, China（科学与工程学院，香港中文大学（深圳））
LEGO: An LLM Skill-Based Front-End Design Generation Platform
School of IC, Peking University（北京大学集成电路学院）；School of EECS, Peking University（北京大学电子信息技术学院）；School of Microelectronics, Xidian University（西安电子科技大学微电子学院）；Institute of EDA, Peking University（北京大学EDA研究院）；Beijing Advanced Innovation Center for IC（北京集成电路先进创新中心）
RTLCurator: Label-Efficient Data Curation for RTL Generation
University of Chinese Academy of Sciences（中国科学院大学）；Hangzhou Institute for Advanced Study, University of Chinese Academy of Sciences（中国科学院大学杭州高等研究院）；Institute of Computing Technology, Chinese Academy of Sciences（中国科学院计算技术研究所）；Computer Network Information Center, Chinese Academy of Sciences（中国科学院计算机网络信息中心）
From Indiscriminate to Targeted: Functionally Critical Signal-Driven Assertion Generation using LLMs for Efficient RTL Verification
State Key Lab of Processors, Institute of Computing Technology, CAS（处理器国家重点实验室，中国科学院计算技术研究所）；University of Chinese Academy of Sciences（中国科学院大学）；Beijing University of Posts and Telecommunications（北京邮电大学）；Beijing Normal University（北京师范大学）；Tencent（腾讯）；The Chinese University of Hong Kong（香港中文大学）
