MasterRTL：面向任意RTL设计的综合前PPA估算框架
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
AI总结：
MasterRTL提出一种综合前PPA估算框架，通过位级简单算子图统一RTL表示，并采用新ML方法分别建模时序、功耗和面积，在90个设计上相比现有方法相关性提升0.33、0.22和0.15。
摘要：
在现代VLSI设计流程中，寄存器传输级（RTL）阶段是一个关键点，设计者使用硬件描述语言（HDL）如Verilog来定义精确的设计行为。由于RTL设计采用HDL代码格式，评估其质量的标准方法需要使用EDA工具进行耗时的后续综合步骤。这一耗时过程严重阻碍了早期RTL阶段的设计优化。尽管近期出现了一些基于机器学习（ML）的解决方案，但它们未能对任意给定的RTL设计保持高精度。在本工作中，我们提出了一种创新的综合前PPA估算框架，名为MasterRTL。它首先将HDL代码转换为一种新的位级设计表示，称为简单算子图（SOG）。通过仅采用单位简单算子，该SOG被证明是一种通用表示，统一了不同的设计类型和风格。SOG也更接近目标门级网表，缩小了RTL表示与网表之间的差距。除了新的SOG表示外，MasterRTL还提出了新的ML方法，分别用于RTL阶段的时序、功耗和面积建模。与最先进的解决方案相比，在包含90个不同设计的综合数据集上的实验显示，总负裕量（TNS）、最差负裕量（WNS）和功耗的相关性分别提高了0.33、0.22和0.15。
英文摘要：
In modern VLSI design flow, the register-transfer level (RTL) stage is a critical point, where designers define precise design behavior with hardware description languages (HDLs) like Verilog. Since the RTL design is in the format of HDL code, the standard way to evaluate its quality requires time-consuming subsequent synthesis steps with EDA tools. This time-consuming process significantly impedes design optimization at the early RTL stage. Despite the emergence of some recent ML-based solutions, they fail to maintain high accuracy for any given RTL design. In this work, we propose an innovative pre-synthesis PPA estimation framework named MasterRTL. It first converts the HDL code to a new bit-level design representation named the simple operator graph (SOG). By only adopting single-bit simple operators, this SOG proves to be a general representation that unifies different design types and styles. The SOG is also more similar to the target gate-level netlist, reducing the gap between RTL representation and netlist. In addition to the new SOG representation, MasterRTL proposes new ML methods for the RTL-stage modeling of timing, power, and area separately. Compared with state-of-the-art solutions, the experiment on a comprehensive dataset with 90 different designs shows accuracy improvement by 0.33, 0.22, and 0.15 in correlation for total negative slack (TNS), worst negative slack (WNS), and power, respectively.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
