AI 中文总结
研究如何在高级综合中对流水线进行细粒度控制以提升硬件设计。提出基于可见性控制的HLS工具，能在顺序编程模型中嵌入控制实现快速设计探索。在多种硬件上评估，结果显示编译后的流水线性能优于同类工具且PPA与手写RTL相当。
AI 中文摘要
高级综合（HLS）将硬件设计的抽象层次从并发寄存器传输级（RTL）程序提升到顺序程序。在HLS利用的并行形式中，流水线需要对流水线结构和冒险解决进行细粒度控制，以实现具有竞争力的功耗、性能和面积（PPA）。然而，现有工具要么缺乏这种控制，要么为了提供控制而牺牲顺序语义。我们提出了一种HLS工具，它在顺序编程模型中嵌入细粒度流水线控制，实现快速的设计空间探索。该工具基于可见性控制，这是一种新颖的编程抽象，统一了包括停顿、旁路、推测、延迟提交和寄存器重命名在内的冒险解决策略。我们在顺序RISC-V内核、直方图和AES加速器上进行评估。在RISC-V内核上，我们实现了停顿、旁路、推测和寄存器重命名；在直方图上，我们实现了以前需要RTL或并发编程模型的调度策略。编译后的流水线优于具有顺序语义的HLS工具，并且实现了与手写RTL相当的PPA。
英文摘要
High-level synthesis (HLS) raises the abstraction of hardware design from concurrent register-transfer level (RTL) programs to sequential programs. Among the forms of parallelism HLS exploits, pipelining demands fine-grained control over pipeline structure and hazard resolution to achieve competitive power, performance, and area (PPA). However, existing tools either lack such control or sacrifice sequential semantics to provide it. We present an HLS tool that embeds fine-grained pipeline control in a sequential programming model, enabling rapid design-space exploration. The tool builds on visibility control, a novel programming abstraction that unifies hazard resolution strategies including stalling, bypassing, speculation, deferred commit, and register renaming. We evaluate on in-order RISC-V cores, histograms, and an AES accelerator. On RISC-V cores, we implement stall, bypass, speculation, and register renaming; on histograms, we implement scheduling strategies that previously required RTL or concurrent programming models. Compiled pipelines outperform HLS tools with sequential semantics and achieve PPA comparable to hand-written RTL.
Comments34 pages
