SCALE：用于先进节点局部布局与布线设计规则违规修复的自监督约束感知布局生成
SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes
浏览论文内容
中文总结 AI 辅助
针对先进节点局部P&R DRV修复难题，提出SCALE框架，通过自监督布局生成、利用自然语言规则约束和高温采样等方法，生成DRC注释布局违规对微调DRC-VLM，有效提升了最先进代理的修复解决率。
中文摘要 AI 辅助
随着半导体制造向2nm以下节点发展，局部布局与布线（P&R）设计规则违规（DRV）修复受到复杂规则交互、密集多层布线几何结构和特定代工厂约束的限制。虽然大语言模型（LLMs）在EDA脚本和文档方面有强大能力，但在视觉布局理解方面应用较少。我们提出SCALE框架，通过自监督布局生成阶段进行先进节点局部DRV修复。将多层布局几何结构序列化到结构化文本中，微调语言模型从周围BEOL上下文重建随机掩码多边形。推理时，自然语言规则约束和高温采样生成多样、易违规的布局变体，经工业签收DRC检查器验证，生成DRC注释的布局违规对用于微调领域适应的DRC-VLM。该VLM为局部DRV修复提供规则感知几何指导，在100个真实2nm以下案例中，将最先进代理的解决率提高12%-25%（最高达97%）。
英文摘要
As semiconductor manufacturing advances toward sub-2nm nodes, local place-and-route (P&R) design-rule violation (DRV) fixing is increasingly limited by complex rule interactions, dense multi-layer routing geometries, and foundry-specific constraints. While Large Language Models (LLMs) have recently demonstrated strong capabilities in EDA scripting and documentation, their application to visual layout understanding remains largely unexplored: diagnosing DRC violations from layout imagery demands precise geometric reasoning and foundry-specific rule knowledge absent from general-purpose VLM training. We propose SCALE, a framework with a self-supervised layout-generation stage for local DRV fixing at advanced nodes. Multi-layer layout geometry is serialized into structured text, and a fine-tuned language model learns to reconstruct randomly masked polygons from surrounding BEOL context alone without violation labels. At inference, natural-language rule constraints and high-temperature sampling steer generation toward diverse, violation-prone layout variants validated by an industrial signoff DRC checker, producing DRC-annotated layout--violation pairs used to fine-tune a domain-adapted DRC-VLM. This VLM provides rule-aware geometric guidance for local DRV repair, boosting state-of-the-art agents' solve rates by +12--25% (up to 97%) on 100 real sub-2nm cases spanning enclosure, spacing, width, and color-spacing violations.
发表机构
- NVIDIA（英伟达）
- Duke University（杜克大学）
机构由 AI 辅助整理，请以论文原文为准。
