Large Language Models (LLMs) have been applied to various hardware design tasks, including Verilog code generation, EDA tool scripting, and RTL bug fixing. Despite this extensive exploration, LLMs are yet to be used for the task of post-synthesis metric reasoning and estimation of HDL designs. In this paper, we assess the ability of LLMs to reason about post-synthesis metrics of Verilog designs. We introduce MetRex, a large-scale dataset comprising 25,868 Verilog HDL designs and their corresponding post-synthesis metrics, namely area, delay, and static power. MetRex incorporates a Chain of Thought (CoT) template to enhance LLMs' reasoning about these metrics. Extensive experiments show that Supervised Fine-Tuning (SFT) boosts the LLM's reasoning capabilities on average by 37.0\%, 25.3\%, and 25.7\% on the area, delay, and static power, respectively. While SFT improves performance on our benchmark, it remains far from achieving optimal results, especially on complex problems. Comparing to state-of-the-art regression models, our approach delivers accurate post-synthesis predictions for 17.4\% more designs (within a 5\% error margin), in addition to offering a 1.7x speedup by eliminating the need for pre-processing. This work lays the groundwork for advancing LLM-based Verilog code metric reasoning.
ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model
National Key Laboratory of Spintronics, Hangzhou International Innovation Institute（国家磁电子重点实验室、杭州国际创新研究院）；School of Integrated Circuit Science and Engineering, Beihang University（集成电路科学与工程学院、北京航空航天大学）
The Cream Rises to the Top: Efficient Reranking Method for Verilog Code Generation
Northwest Polytechnical University, Shaanxi, China（西北工业大学）；Nantong University, Jiangsu, China（南通大学）；Minzu University of China, Beijing, China（中央民族大学）；City University of Hong Kong, Hong Kong, China（香港城市大学）；Monash University, Victoria, Australia（墨尔本大学）
Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT
State Key Lab of Processors, Institute of Computing Technology, CAS（处理器重点实验室，计算技术研究所，中国科学院）；University of Chinese Academy of Sciences（中国科学院大学）；Beijing Normal University（北京师范大学）；Peking University（北京大学）；Chinese University of Hong Kong（香港中文大学）
Execution-Anchored Hallucination Calibration Reranking for Verilog Code Generation
State Key Laboratory of Blockchain and Data Security, Zhejiang University（浙江大学区块链与数据安全全国重点实验室）；Hangzhou High-Tech Zone (Binjiang) Institute of Blockchain and Data Security（杭州国家高新区（滨江）区块链与数据安全研究院）；School of Artificial Intelligence and Computer Science, Nantong University（南通大学人工智能与计算机学院）；Department of Computer Science, Monash University（蒙纳士大学计算机科学系）；CSIRO’s Data61（澳大利亚联邦科学与工业研究组织数据61）
EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code
Department of Computer Science, City University of Hong Kong, Hong Kong（香港城市大学计算机科学系）；Department of Electrical Engineering, University of Maryland, Maryland, United States（马里兰大学电气工程系）；Amazon, Seattle, United States（亚马逊公司）
VeriPilot: An LLM-Powered Verilog Debugging Framework
State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences（中国科学院计算技术研究所国家专用集成电路设计实验室）；University of Chinese Academy of Sciences（中国科学院大学）；North China Electric Power University（华北电力大学）
