噪声增强的混沌伊辛机用于组合优化与采样
Noise-augmented Chaotic Ising Machines for Combinatorial Optimization and Sampling
AI总结：
本文提出噪声增强的混沌伊辛机，通过向混沌比特注入随机性提升组合优化与采样性能，实现与概率比特相当的扩展性，并优于确定性模拟退火算法。
摘要：
伊辛机是用于组合优化和概率采样问题的硬件加速器，近年来引起了广泛关注。其关键要素是随机性，它能够实现对配置的广泛探索，从而有助于避免局部最小值。在此，我们改进了先前提出的无显式随机性运行的耦合混沌比特（c-bits）概念。我们表明，向混沌比特添加随机性可提升组合优化的性能，实现与概率比特（p-bits）相当的算法扩展性。我们首先证明，在一维横向场伊辛模型中，c-bits遵循量子玻尔兹曼定律。然后，我们展示在二维伊辛和三维自旋玻璃模型中，c-bits表现出与随机p-bits类似的临界动力学，具有解决具有挑战性的优化问题的潜力。最后，我们通过自适应并行回火算法（APT）提出了一种噪声增强的耦合c-bits版本。我们的噪声增强c-bit算法优于运行模拟退火算法的完全确定性c-bits。其他具有耦合振荡器的模拟伊辛机可以从所提出的算法中汲取灵感。在恒定温度下运行副本消除了对耦合强度进行全局调制的需求。将随机性与确定性c-bits混合，创造了一种强大的混合计算方案，可在规模化、异步和大规模并行硬件实现中带来益处。
英文摘要：
Ising machines, hardware accelerators for combinatorial optimization and probabilistic sampling problems, have gained significant interest recently. A key element is stochasticity, which enables a wide exploration of configurations, thereby helping avoid local minima. Here, we refine the previously proposed concept of coupled chaotic bits (c-bits) that operate without explicit stochasticity. We show that augmenting chaotic bits with stochasticity enhances performance in combinatorial optimization, achieving algorithmic scaling comparable to probabilistic bits (p-bits). We first demonstrate that c-bits follow the quantum Boltzmann law in a 1D transverse field Ising model. We then show that c-bits exhibit critical dynamics similar to stochastic p-bits in 2D Ising and 3D spin glass models, with promising potential to solve challenging optimization problems. Finally, we propose a noise-augmented version of coupled c-bits via the adaptive parallel tempering algorithm (APT). Our noise-augmented c-bit algorithm outperforms fully deterministic c-bits running versions of the simulated annealing algorithm. Other analog Ising machines with coupled oscillators could draw inspiration from the proposed algorithm. Running replicas at constant temperature eliminates the need for global modulation of coupling strengths. Mixing stochasticity with deterministic c-bits creates a powerful hybrid computing scheme that can bring benefits in scaled, asynchronous, and massively parallel hardware implementations.
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