arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2407.08473cs.ARcs.AI
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自然语言还不够:面向Verilog生成的多模态生成AI基准测试

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation

Institute of Computing Technology, Chinese Academy of Sciences(中国科学院计算技术研究所);University of Chinese Academy of Sciences(中国科学院大学);Hangzhou Institute for Advanced Study, University of Chinese Academy of Sciences(中国科学院大学杭州高等研究院);Shanghai Jiao Tong University(上海交通大学)

Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, kun wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang

AI总结:

该研究指出视觉信息对硬件设计的重要性,提出面向Verilog生成的多模态生成AI开源基准与查询框架,实验证明其准确率显著优于纯自然语言方法,为硬件设计提供新路径。

摘要:

自然语言接口借助大语言模型在从高层规格说明自动生成Verilog代码方面展现出巨大潜力,受到了广泛关注。然而本文阐明,对于具有空间复杂性的硬件架构,视觉表征能提供对设计意图至关重要的关键上下文信息,其效果可能超越仅使用自然语言的输入。基于这一前提,本文提出了一个面向多模态生成模型的开源基准,专门用于从视觉-语言输入合成Verilog代码,覆盖单一模块和复杂模块两类场景。此外,我们还推出了一个开源的视觉与自然语言Verilog查询语言框架,以支持高效且易用的多模态查询。为评估所提出的多模态硬件生成AI在Verilog生成任务中的性能,我们将其与一种仅依赖自然语言的主流方法进行了对比。结果表明,与仅基于自然语言的查询生成结果相比,多模态生成的Verilog代码在准确率上有显著提升。我们希望借此揭示大硬件设计模型时代硬件设计的新路径,从而推动硬件设计向更多元化、更高效的方向发展。

英文摘要:

Natural language interfaces have exhibited considerable potential in the automation of Verilog generation derived from high-level specifications through the utilization of large language models, garnering significant attention. Nevertheless, this paper elucidates that visual representations contribute essential contextual information critical to design intent for hardware architectures possessing spatial complexity, potentially surpassing the efficacy of natural-language-only inputs. Expanding upon this premise, our paper introduces an open-source benchmark for multi-modal generative models tailored for Verilog synthesis from visual-linguistic inputs, addressing both singular and complex modules. Additionally, we introduce an open-source visual and natural language Verilog query language framework to facilitate efficient and user-friendly multi-modal queries. To evaluate the performance of the proposed multi-modal hardware generative AI in Verilog generation tasks, we compare it with a popular method that relies solely on natural language. Our results demonstrate a significant accuracy improvement in the multi-modal generated Verilog compared to queries based solely on natural language. We hope to reveal a new approach to hardware design in the large-hardware-design-model era, thereby fostering a more diversified and productive approach to hardware design.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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