使用Verilog到布线工具链对StreamNTT进行基准测试
Benchmarking StreamNTT with a Verilog-to-Routing Toolchain
- Rochester Institute of Technology（罗切斯特理工学院）
- Inha University（仁荷大学）
机构由 AI 辅助整理，请以论文原文为准。
AI总结：
针对StreamNTT依赖商业工具难以复现的问题，本文在开源Verilog到布线工具链上构建并基准测试，验证了相似DSP和乘法器使用，但指出内存利用需进一步优化。
AI中文摘要：
随着后量子密码算法向大规模数据中心部署推进，对其计算瓶颈——数论变换（NTT）——的硬件加速日益受到关注。StreamNTT是一种基于高层次综合和现场可编程门阵列的加速器，通过多种优化技术实现了最先进的吞吐量。然而，其对商业工具和设备的依赖使得无法使用这些资源的研究人员难以进行直接比较。我们通过在开源Verilog到布线工具链上构建StreamNTT来解决这一问题，该工具链实现了相似的数字信号处理和乘法器使用量。内部存储器利用率的显著差异表明，需要进一步的存储器级优化以接近商业工具的性能。
英文摘要：
As post-quantum cryptography algorithms move toward large-scale data center deployment, hardware acceleration of their computational bottleneck, which is the number theoretic transform (NTT), has gained increasing attention. StreamNTT, a high-level synthesis- and field-programmable gate array-based accelerator, achieves state-of-the-art throughput through various optimization techniques. However, its reliance on a commercial tool and a device makes direct comparisons difficult for researchers without access. We address this by building StreamNTT on an open-source Verilog-to-Routing toolchain, which achieves similar digital signal processing and multiplier usage. Significant differences in internal memory utilization indicate that further memory-level optimization is needed to approach commercial tool performance.
