针对抗辐射TMR寄存器的激光故障注入攻击

基于近似计算的容错设计方法

Fault-Tolerant Design Approach Based on Approximate Computing

本文提出基于近似计算的容错设计方法FAC，在保持与三模冗余TMR相同容错能力的同时，显著降低延迟、面积和功耗开销，并通过28纳米CMOS图像处理应用验证其有效性。

X-Rel：面向关键系统中部署的容错应用的高能效低开销近似可靠性框架

X-Rel: Energy-Efficient and Low-Overhead Approximate Reliability Framework for Error-Tolerant Applications Deployed in Critical Systems

本文提出X-Rel框架，通过系统化误差界定方法放宽表决器精度并据此近似TMR模块，在满足用户定义的可靠性与质量约束下显著降低关键系统中容错应用的延迟、面积和能耗。

Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation

Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bottleneck for future GPUs due to long access latency, high power consumption, and large silicon area provisioning. Prior work proposes hierarchical register file to reduce the register file power consumption by caching registers in a smaller register file cache. Unfortunately, this approach does not improve register access latency due to the low hit rate in the register file cache. In this paper, we propose the Latency…

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections between signals from distinct redundant logic parts, which can generate an error in the output. This paper investigates the optimal design of the TMR logic (e.g., by cleverly inserting voters) to ensure robustness. Four different versions of a TMR digital filter were analyzed by fault injection. Faults we…

A Fault-tolerant Structure for Reliable Multi-core Systems Based on Hardware-Software Co-design

To cope with the soft errors and make full use of the multi-core system, this paper gives an efficient fault-tolerant hardware and software co-designed architecture for multi-core systems. And with a not large number of test patterns, it will use less than 33% hardware resources compared with the traditional hardware redundancy (TMR) and it will take less than 50% time compared with the traditional software redundancy (time redundant).Therefore, it will be a good choice for the fault-tolerant architecture for the future high-reliable multi-core systems.

A Fault Tolerance Improved Majority Voter for TMR System Architectures

For digital system designs, triple modular redundancy (TMR), which is a 3-tuple version of N-modular redundancy is widely preferred for many mission-control and safety-critical applications. The TMR scheme involves two-times duplication of the simplex system hardware, with a majority voter ensuring correctness provided at least two out of three copies of the system remain operational. Thus the majority voter plays a pivotal role in ensuring the correct operation of the system. The fundamental assumption implicit in the TMR scheme is that the majority voter does not become faulty, which may not…