采用130nm SiGe BiCMOS工艺的1.8μm间距、47ps抖动SPAD阵列
A 1.8-um pitch, 47-ps jitter SPAD Array in 130nm SiGe BiCMOS Process
AI总结：
本文提出首个130nm SiGe BiCMOS工艺SPAD系列，通过保护环共享实现1.8μm间距与24.2%填充因子，并验证其低抖动、高PDP及阵列可扩展性。
摘要：
我们介绍了全球首个采用130 nm SiGe BiCMOS工艺的SPAD系列设计。在1.8μm下，得益于保护环共享技术，我们实现了有记录以来的最小间距，同时保持了24.2%的相对较高填充因子。设计了带有两个并行选择性读出电路的4×4 SPAD阵列，以研究串扰和可扩展性。该SPAD系列的最低击穿电压为11 V，最大PDP为40.6%，典型时序抖动为47 ps FWHM。SiGe工艺中硅SPAD的发展为面向SWIR应用的Ge-on-Si SPAD以及面向量子应用的低温光学接口铺平了道路。
英文摘要：
We introduce the world's first SPAD family design in 130 nm SiGe BiCMOS process. At 1.8um, we achieved the smallest pitch on record thanks to guard-ring sharing techniques, while keeping a relatively high fill factor of 24.2%. 4x4 SPAD arrays with two parallel selective readout circuits were designed to explore crosstalk and scalability. The SPAD family has a minimum breakdown voltage of 11 V, a maximum PDP of 40.6% and a typical timing jitter of 47 ps FWHM. The development of silicon SPADs in SiGe process paves the way to Ge-on-Si SPADs for SWIR applications, and to cryogenic optical interfaces for quantum applications.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
